Merge tag 'timers-clocksource-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull clocksource updates from Thomas Gleixner:

- Further preparations for modular clocksource/eve

Merge tag 'timers-clocksource-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull clocksource updates from Thomas Gleixner:

- Further preparations for modular clocksource/event drivers

- The usual device tree updates to support new chip variants and the
related changes to thise drivers

- Avoid a 64-bit division in the TEGRA186 driver, which caused a build
fail on 32-bit machines.

- Small fixes, improvements and cleanups all over the place

* tag 'timers-clocksource-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits)
dt-bindings: timer: exynos4210-mct: Add compatible for ARTPEC-9 SoC
clocksource/drivers/sh_cmt: Split start/stop of clock source and events
clocksource/drivers/clps711x: Fix resource leaks in error paths
clocksource/drivers/arm_global_timer: Add auto-detection for initial prescaler values
clocksource/drivers/ingenic-sysost: Convert from round_rate() to determine_rate()
clocksource/drivers/timer-tegra186: Don't print superfluous errors
clocksource/drivers/timer-rtl-otto: Simplify documentation
clocksource/drivers/timer-rtl-otto: Do not interfere with interrupts
clocksource/drivers/timer-rtl-otto: Drop set_counter function
clocksource/drivers/timer-rtl-otto: Work around dying timers
clocksource/drivers/timer-ti-dm : Capture functionality for OMAP DM timer
clocksource/drivers/arm_arch_timer_mmio: Add MMIO clocksource
clocksource/drivers/arm_arch_timer_mmio: Switch over to standalone driver
clocksource/drivers/arm_arch_timer: Add standalone MMIO driver
ACPI: GTDT: Generate platform devices for MMIO timers
clocksource/drivers/nxp-pit: Add NXP Automotive s32g2 / s32g3 support
dt: bindings: fsl,vf610-pit: Add compatible for s32g2 and s32g3
clocksource/drivers/vf-pit: Rename the VF PIT to NXP PIT
clocksource/drivers/vf-pit: Unify the function name for irq ack
clocksource/drivers/vf-pit: Consolidate calls to pit_*_disable/enable
...

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Merge tag 'timers-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/daniel.lezcano/linux into timers/clocksource

Pull clocksource/events driver updates from Daniel Lezcano:

- Add the m

Merge tag 'timers-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/daniel.lezcano/linux into timers/clocksource

Pull clocksource/events driver updates from Daniel Lezcano:

- Add the module owner to all the drivers which can be converted into
modules in order to have the core time framework to take the
refcount and prevent wild module removal. In addition export the
symbols for the sched_clock_register() function to allow the drivers
to be converted into modules (Daniel Lezcano)

- Convert the faraday,fttmr010 DT bindings to yaml schema (Rob
Herring)

- Add the DT bindings compatible string for the MT6572 (Max
Shevchenko)

- Fix the fsl,ftm-timer bindings by using the items to describe a
register (Frank Li)

- Add the DT binding documentation for Andes machine timer (Ben
Zong-You Xie)

- Avoid 64-bit divide operation which fails on xtensa and simplify the
timeleft computation with 32 bits operations on Tegra186 (Guenter
Roeck)

- Add the fsl,timrot.yaml DT bindings for i.MX23/i.MX28 timer (Frank
Li)

- Replace comma by semicolon which were introduced when moving the
static structure initialization (Chen Ni)

- Add a new compatible for the MediaTek MT8196 SoC, fully compatible
with MT6765 (AngeloGioacchino Del Regno)

- Add the support for the s32g2 and s32g3 platforms in the PIT timer
after cleaning up the code to support multiple instances (Daniel
Lezcano)

- Generate platform devices for MMIO timers with ACPI and integrate it
with the arch ARM timer (Marc Zyngier)

- Fix RTL OTTO timer by working around dying timers (Markus Stockhausen)

- Remove extra error message in the tegra186 timer (Wolfram Sang)

- Convert from round_rate() to determine_rate() in the Ingenic sysost
driver (Brian Masney)

- Add PWM capture functionality in the OMAP DM driver (Gokul Praveen)

- Autodetect the clock rate to initialize a prescaler value compatible
with the frequency changes on the ARM global timer (Markus
Schneider-Pargmann)

- Fix rollbacks missing resource deallocation in case of error on the
clps711x (Zhen Ni)

- Reorganize the code to split the start and the stop routine on the
sh_cmt driver (Niklas Söderlund)

- Add the compatible definition for ARTPEC-9 on exynos MCT (SungMin Park)

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clocksource/drivers/nxp-pit: Add NXP Automotive s32g2 / s32g3 support

The previous changes put in place the encapsulation of the code in
order to allow multiple instances of the driver.

The S32G pl

clocksource/drivers/nxp-pit: Add NXP Automotive s32g2 / s32g3 support

The previous changes put in place the encapsulation of the code in
order to allow multiple instances of the driver.

The S32G platform has two Periodic Interrupt Timer (PIT). The IP is
exactly the same as the VF platform.

Each PIT has four channels which are 32 bits wide and counting
down. The two first channels can be chained to implement a 64 bits
counter. The channel usage is kept unchanged with the original driver,
channel 2 is used as a clocksource, channel 3 is used as a
clockevent. Other channels are unused.

In order to support the S32G platform which has two PIT, we initialize
the timer and bind it to a CPU. The S32G platforms can have 2, 4 or 8
CPUs and this kind of configuration can appear unusual as we may endup
with two PIT used as a clockevent for the two first CPUs while the
other CPUs use the architected timers. However, in the context of the
automotive, the platform can be partioned to assign 2 CPUs for Linux
and the others CPUs to third party OS. The PIT is then used with their
specifities like the ability to freeze the time which is needed for
instance for debugging purpose.

The setup found for this platform is each timer instance is bound to
CPU0 and CPU1.

A counter is incremented when a timer is successfully initialized and
assigned to a CPU. This counter is used as an index for the CPU number
and to detect when we reach the maximum possible instances for the
platform. That in turn triggers the CPU hotplug callbacks to achieve
the per CPU setup. It is the exact same mechanism found in the NXP STM
driver.

If the timers must be bound to different CPUs, it would require an
additionnal mechanism which is not part of these changes.

Tested on a s32g274a-rdb2.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20250804152344.1109310-21-daniel.lezcano@linaro.org

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clocksource/drivers/vf-pit: Rename the VF PIT to NXP PIT

The PIT acronym stands for Periodic Interrupt Timer which is found on
different NXP platforms not only on the Vybrid Family. Change the name

clocksource/drivers/vf-pit: Rename the VF PIT to NXP PIT

The PIT acronym stands for Periodic Interrupt Timer which is found on
different NXP platforms not only on the Vybrid Family. Change the name
to be more generic for the NXP platforms in general. That will be
consistent with the NXP STM driver naming convention.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20250804152344.1109310-19-daniel.lezcano@linaro.org

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