1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright 2012-2013 Freescale Semiconductor, Inc.
4  * Copyright 2018,2021-2025 NXP
23 #define PITMCR_FRZ	BIT(0)
24 #define PITMCR_MDIS	BIT(1)
32 #define PITTCTRL_TEN			BIT(0)
33 #define PITTCTRL_TIE			BIT(1)
37 #define PITTFLG_TIF			BIT(0)
43 	struct clocksource cs;  member
66 static inline struct pit_timer *cs_to_pit(struct clocksource *cs)  in cs_to_pit()  argument
68 	return container_of(cs, struct pit_timer, cs);  in cs_to_pit()
100 	writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base));  in pit_timer_irqack()
108 static u64 pit_timer_clocksource_read(struct clocksource *cs)  in pit_timer_clocksource_read()  argument
110 	struct pit_timer *pit = cs_to_pit(cs);  in pit_timer_clocksource_read()
112 	return (u64)~readl(PITCVAL(pit->clksrc_base));  in pit_timer_clocksource_read()
119 	 * The channels 0 and 1 can be chained to build a 64-bit  in pit_clocksource_init()
123 	pit->clksrc_base = base + PIT_CH(2);  in pit_clocksource_init()
124 	pit->cs.name = name;  in pit_clocksource_init()
125 	pit->cs.rating = 300;  in pit_clocksource_init()
126 	pit->cs.read = pit_timer_clocksource_read;  in pit_clocksource_init()
127 	pit->cs.mask = CLOCKSOURCE_MASK(32);  in pit_clocksource_init()
128 	pit->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;  in pit_clocksource_init()
130 	/* set the max load value and start the clock source counter */  in pit_clocksource_init()
131 	pit_timer_disable(pit->clksrc_base);  in pit_clocksource_init()
132 	pit_timer_set_counter(pit->clksrc_base, ~0);  in pit_clocksource_init()
133 	pit_timer_enable(pit->clksrc_base, 0);  in pit_clocksource_init()
135 	sched_clock_base = pit->clksrc_base + PITCVAL_OFFSET;  in pit_clocksource_init()
138 	return clocksource_register_hz(&pit->cs, rate);  in pit_clocksource_init()
146 	 * set a new value to PITLDVAL register will not restart the timer,  in pit_set_next_event()
148 	 * value, the timer must be disabled and enabled again.  in pit_set_next_event()
152 	pit_timer_disable(pit->clkevt_base);  in pit_set_next_event()
153 	pit_timer_set_counter(pit->clkevt_base, delta - 1);  in pit_set_next_event()
154 	pit_timer_enable(pit->clkevt_base, true);  in pit_set_next_event()
163 	pit_timer_disable(pit->clkevt_base);  in pit_shutdown()
172 	pit_set_next_event(pit->rate / HZ, ced);  in pit_set_periodic()
186 	 * and reload the counter value from PITLDVAL when PITCVAL reach zero,  in pit_timer_interrupt()
191 		pit_timer_disable(pit->clkevt_base);  in pit_timer_interrupt()
193 	ced->event_handler(ced);  in pit_timer_interrupt()
205 	 * The channels 0 and 1 can be chained to build a 64-bit  in pit_clockevent_per_cpu_init()
209 	pit->clkevt_base = base + PIT_CH(3);  in pit_clockevent_per_cpu_init()
210 	pit->rate = rate;  in pit_clockevent_per_cpu_init()
212 	pit_timer_disable(pit->clkevt_base);  in pit_clockevent_per_cpu_init()
217 			  name, &pit->ced);  in pit_clockevent_per_cpu_init()
221 	pit->ced.cpumask = cpumask_of(cpu);  in pit_clockevent_per_cpu_init()
222 	pit->ced.irq = irq;  in pit_clockevent_per_cpu_init()
224 	pit->ced.name = name;  in pit_clockevent_per_cpu_init()
225 	pit->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;  in pit_clockevent_per_cpu_init()
226 	pit->ced.set_state_shutdown = pit_shutdown;  in pit_clockevent_per_cpu_init()
227 	pit->ced.set_state_periodic = pit_set_periodic;  in pit_clockevent_per_cpu_init()
228 	pit->ced.set_next_event	= pit_set_next_event;  in pit_clockevent_per_cpu_init()
229 	pit->ced.rating	= 300;  in pit_clockevent_per_cpu_init()
238 	pit_timer_disable(pit->clkevt_base);  in pit_clockevent_per_cpu_exit()
239 	free_irq(pit->ced.irq, &pit->ced);  in pit_clockevent_per_cpu_exit()
251 	ret = irq_force_affinity(pit->ced.irq, cpumask_of(cpu));  in pit_clockevent_starting_cpu()
258 	 * The value for the LDVAL register trigger is calculated as:  in pit_clockevent_starting_cpu()
259 	 * LDVAL trigger = (period / clock period) - 1  in pit_clockevent_starting_cpu()
260 	 * The pit is a 32-bit down count timer, when the counter value  in pit_clockevent_starting_cpu()
262 	 * LDVAL trigger value is 1. And then the min_delta is  in pit_clockevent_starting_cpu()
263 	 * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.  in pit_clockevent_starting_cpu()
265 	clockevents_config_and_register(&pit->ced, pit->rate, 2, 0xffffffff);  in pit_clockevent_starting_cpu()
281 		return -ENOMEM;  in pit_timer_init()
283 	ret = -ENXIO;  in pit_timer_init()
290 	ret = -EINVAL;  in pit_timer_init()
338 	clocksource_unregister(&pit->cs);  in pit_timer_init()
358 	pit_timer_data = of_device_get_match_data(&pdev->dev);  in pit_timer_probe()
360 		max_pit_instances = pit_timer_data->max_pit_instances;  in pit_timer_probe()
362 	return pit_timer_init(pdev->dev.of_node);  in pit_timer_probe()
368 	{ .compatible = "nxp,s32g2-pit", .data = &s32g2_data },
375 		.name = "nxp-pit",
382 TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);