Lines Matching +full:cs +full:- +full:value +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0 */
7  *	15 Sept 2005 Eric Biederman: 64bit PIC support
9  *	Entry: CS:IP point to the start of our code, we are
15  *	with 16-bit addressing and 16-bit data.  CS has some value
20  *	now enter a 64bit kernel that lives at arbitrary 64bit
24  *	--full-contents --reloc to make sure there are no relocation
33 #include <asm/processor-flags.h>
67 	mov	%cs, %ax	# Code and data in the same place
82 	 * operand size is 16bit. Use lgdtl instead to force operand size
83 	 * to 32 bit.
104 /* SEV-ES supports non-zero IP for entry points - no alignment needed */
110 	mov	%cs, %ax	# Code and data in the same place
136 	 * case BIOS hasn't done the necessary step of setting the bit in
138 	 * then it is safe for us to set the MSR bit and continue. If we
150 	 * Memory encryption is enabled but the SME enable bit for this
168 	 * value (to avoid #VE for the TDX guest).
185 	 * At this point we're in long mode but in 32bit compatibility mode
186 	 * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
187 	 * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
188 	 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
196 	 * paging and complete the switch to legacy 32-bit mode.
216 	 * APs start here on a direct transfer from 64-bit BIOS with identity
218 	 * 32-bit mode (to handle 4-level vs. 5-level paging), and to (re)load
231 	/* Paging mode is correct proceed in 64-bit mode */
251 	 * To switch between 4- and 5-level paging modes, it is necessary
262 	.short	tr_gdt_end - tr_gdt - 1	# gdt limit
271 	.short	tr_gdt_end - tr_gdt - 1	# gdt limit