Lines Matching +full:cs +full:- +full:value +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
18 #define DEVICE_RESET__BANK(bank) BIT(bank)
21 #define TRANSFER_SPARE_REG__FLAG BIT(0)
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank)
39 #define MULTIPLANE_OPERATION__FLAG BIT(0)
42 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
45 #define COPYBACK_DISABLE__FLAG BIT(0)
48 #define CACHE_WRITE_ENABLE__FLAG BIT(0)
51 #define CACHE_READ_ENABLE__FLAG BIT(0)
54 #define PREFETCH_MODE__PREFETCH_EN BIT(0)
58 #define CHIP_EN_DONT_CARE__FLAG BIT(0)
61 #define ECC_ENABLE__FLAG BIT(0)
64 #define GLOBAL_INT_EN_FLAG BIT(0)
71 /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
97 #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
100 #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
144 #define WRITE_PROTECT__FLAG BIT(0)
187 #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
198 #define FEATURES__DMA BIT(6)
199 #define FEATURES__CMD_DMA BIT(7)
200 #define FEATURES__PARTITION BIT(8)
201 #define FEATURES__XDMA_SIDEBAND BIT(9)
202 #define FEATURES__GPREG BIT(10)
203 #define FEATURES__INDEX_ADDR BIT(11)
210 /* bit[1:0] is used differently depending on IP version */
211 #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
212 #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
213 #define INTR__ECC_ERR BIT(1) /* old IP */
214 #define INTR__DMA_CMD_COMP BIT(2)
215 #define INTR__TIME_OUT BIT(3)
216 #define INTR__PROGRAM_FAIL BIT(4)
217 #define INTR__ERASE_FAIL BIT(5)
218 #define INTR__LOAD_COMP BIT(6)
219 #define INTR__PROGRAM_COMP BIT(7)
220 #define INTR__ERASE_COMP BIT(8)
221 #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
222 #define INTR__LOCKED_BLK BIT(10)
223 #define INTR__UNSUP_CMD BIT(11)
224 #define INTR__INT_ACT BIT(12)
225 #define INTR__RST_COMP BIT(13)
226 #define INTR__PIPE_CMD_ERR BIT(14)
227 #define INTR__PAGE_XFER_INC BIT(15)
228 #define INTR__ERASED_PAGE BIT(16)
251 #define ERR_CORRECTION_INFO__UNCOR BIT(14)
252 #define ERR_CORRECTION_INFO__LAST_ERR BIT(15)
257 #define ECC_COR_INFO__UNCOR_ERR BIT(7)
268 #define DMA_ENABLE__FLAG BIT(0)
271 #define IGNORE_ECC_DONE__FLAG BIT(0)
275 #define DMA_INTR__TARGET_ERROR BIT(0)
276 #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
277 #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
278 #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
279 #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
280 #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
289 #define CHNL_ACTIVE__CHANNEL0 BIT(0)
290 #define CHNL_ACTIVE__CHANNEL1 BIT(1)
291 #define CHNL_ACTIVE__CHANNEL2 BIT(2)
292 #define CHNL_ACTIVE__CHANNEL3 BIT(3)
295 * struct denali_chip_sel - per-CS data of Denali NAND
297 * @bank: bank id of the controller this CS is connected to
298 * @hwhr2_and_we_2_re: value of timing register HWHR2_AND_WE_2_RE
299 * @tcwaw_and_addr_2_data: value of timing register TCWAW_AND_ADDR_2_DATA
300 * @re_2_we: value of timing register RE_2_WE
301 * @acc_clks: value of timing register ACC_CLKS
302 * @rdwr_en_lo_cnt: value of timing register RDWR_EN_LO_CNT
303 * @rdwr_en_hi_cnt: value of timing register RDWR_EN_HI_CNT
304 * @cs_setup_cnt: value of timing register CS_SETUP_CNT
305 * @re_2_re: value of timing register RE_2_RE
320 * struct denali_chip - per-chip data of Denali NAND
324 * @nsels: the number of CS lines of this chip
325 * @sels: the array of per-cs data
335 * struct denali_controller - Denali NAND controller data
355 * @caps: controller capabilities that cannot be detected run-time
389 #define DENALI_CAP_HW_ECC_FIXUP BIT(0)
390 #define DENALI_CAP_DMA_64BIT BIT(1)