1 // SPDX-License-Identifier: GPL-2.0-only
5  *  Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
18 #define  NAND_WAIT_RD		BIT(0) /* NAND flash status output */
19 #define  NAND_WAIT_WR_C		BIT(3) /* NAND Write/Read complete */
28  * correct line. For example when the bit (1 << 2) is set in the address
31 #define NAND_CMD_ALE		BIT(2) /* address latch enable */
32 #define NAND_CMD_CLE		BIT(3) /* command latch enable */
33 #define NAND_CMD_CS		BIT(4) /* chip select */
34 #define NAND_CMD_SE		BIT(5) /* spare area access latch */
35 #define NAND_CMD_WP		BIT(6) /* write protect */
76 	return readb(data->nandaddr + op);  in xway_readb()
79 static void xway_writeb(struct mtd_info *mtd, int op, u8 value)  in xway_writeb()  argument
84 	writeb(value, data->nandaddr + op);  in xway_writeb()
92 	case -1:  in xway_select_chip()
95 		spin_unlock_irqrestore(&ebu_lock, data->csflags);  in xway_select_chip()
98 		spin_lock_irqsave(&ebu_lock, data->csflags);  in xway_select_chip()
151 	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&  in xway_attach_chip()
152 	    chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)  in xway_attach_chip()
153 		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;  in xway_attach_chip()
170 	u32 cs;  in xway_nand_probe()  local
174 	data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),  in xway_nand_probe()
177 		return -ENOMEM;  in xway_nand_probe()
179 	data->nandaddr = devm_platform_ioremap_resource(pdev, 0);  in xway_nand_probe()
180 	if (IS_ERR(data->nandaddr))  in xway_nand_probe()
181 		return PTR_ERR(data->nandaddr);  in xway_nand_probe()
183 	nand_set_flash_node(&data->chip, pdev->dev.of_node);  in xway_nand_probe()
184 	mtd = nand_to_mtd(&data->chip);  in xway_nand_probe()
185 	mtd->dev.parent = &pdev->dev;  in xway_nand_probe()
187 	data->chip.legacy.cmd_ctrl = xway_cmd_ctrl;  in xway_nand_probe()
188 	data->chip.legacy.dev_ready = xway_dev_ready;  in xway_nand_probe()
189 	data->chip.legacy.select_chip = xway_select_chip;  in xway_nand_probe()
190 	data->chip.legacy.write_buf = xway_write_buf;  in xway_nand_probe()
191 	data->chip.legacy.read_buf = xway_read_buf;  in xway_nand_probe()
192 	data->chip.legacy.read_byte = xway_read_byte;  in xway_nand_probe()
193 	data->chip.legacy.chip_delay = 30;  in xway_nand_probe()
195 	nand_controller_init(&data->controller);  in xway_nand_probe()
196 	data->controller.ops = &xway_nand_ops;  in xway_nand_probe()
197 	data->chip.controller = &data->controller;  in xway_nand_probe()
200 	nand_set_controller_data(&data->chip, data);  in xway_nand_probe()
202 	/* load our CS from the DT. Either we find a valid 1 or default to 0 */  in xway_nand_probe()
203 	err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs);  in xway_nand_probe()
204 	if (!err && cs == 1)  in xway_nand_probe()
208 	ltq_ebu_w32(CPHYSADDR(data->nandaddr)  in xway_nand_probe()
221 	 * Set ->engine_type before registering the NAND devices in order to  in xway_nand_probe()
222 	 * provide a driver specific default value.  in xway_nand_probe()
224 	data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;  in xway_nand_probe()
227 	err = nand_scan(&data->chip, 1);  in xway_nand_probe()
233 		nand_cleanup(&data->chip);  in xway_nand_probe()
244 	struct nand_chip *chip = &data->chip;  in xway_nand_remove()
253 	{ .compatible = "lantiq,nand-xway" },
261 		.name		= "lantiq,nand-xway",