| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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| /freebsd/share/man/man3/ |
| H A D | qmath.3 | 31 .Nd fixed-point math library based on the
39 data types and APIs support fixed-point math based on the
79 None of the operations is affected by the floating-point environment.
86 .Bl -column "isgreaterequal" "bessel function of the second kind of the order 0"
134 .Ss Functions which manipulate the control/sign data bits
136 .Xr Q_SIGNSHFT 3 sign bit position
137 .Xr Q_SSIGN 3 sign bit
138 .Xr Q_CRAWMASK 3 control bitmask
140 .Xr Q_GCRAW 3 raw control bits
141 .Xr Q_GCVAL 3 value of control bits
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| H A D | Q_SIGNSHFT.3 | 37 .Nd fixed-point math functions which manipulate the control/sign data bits
56 gets the bit position of
58 sign bit relative to bit zero.
61 sets the sign bit of
70 .Fa q Ns -specific
73 control bits and sign bit respectively.
78 get the raw masked control bits and value of
80 control bits respectively.
85 control bits to the value
111 returns the sign bit's position as an integer.
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| /freebsd/contrib/wpa/src/common/ |
| H A D | wpa_ctrl.h | 2 * wpa_supplicant/hostapd control interface library
3 * Copyright (c) 2004-2017, Jouni Malinen <j@w1.fi>
16 /* wpa_supplicant control interface - fixed message prefixes */
19 #define WPA_CTRL_REQ "CTRL-REQ-"
22 #define WPA_CTRL_RSP "CTRL-RSP-"
26 #define WPA_EVENT_CONNECTED "CTRL-EVENT-CONNECTED "
28 #define WPA_EVENT_DISCONNECTED "CTRL-EVENT-DISCONNECTED "
30 #define WPA_EVENT_ASSOC_REJECT "CTRL-EVENT-ASSOC-REJECT "
32 #define WPA_EVENT_AUTH_REJECT "CTRL-EVENT-AUTH-REJECT "
34 #define WPA_EVENT_TERMINATING "CTRL-EVENT-TERMINATING "
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| /freebsd/sys/contrib/dev/athk/ath12k/ |
| H A D | rx_desc.h | 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
27 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7)
28 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8)
29 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9)
30 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10)
33 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17)
34 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18)
35 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19)
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | spear_spics.txt | 3 SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
5 PL022 control. If chipselect remain under PL022 control then they would be
12 directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
13 the control of this interface as gpio.
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | lp872x.txt | 4 - compatible: "ti,lp8720" or "ti,lp8725"
5 - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
12 bit[1]: sleep control by external DVS pin or register
14 bit[0]: time step unit(usec). 1 = 25, 0 = 50
17 bit[7:6]: time step unit(usec). 00 = 32, 01 = 64, 10 = 128, 11 = 256
18 bit[4]: BUCK2 enable control. 1 = enable, 0 = disable
19 bit[3]: BUCK2 output voltage register address. 1 = 0Ah, 0 = 0Bh
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
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| /freebsd/sys/dev/sfxge/common/ |
| H A D | efx_regs_pci.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
41 * PC_VEND_ID_REG(16bit):
52 * PC_DEV_ID_REG(16bit):
63 * PC_CMD_REG(16bit):
94 * PC_STAT_REG(16bit):
125 * PC_REV_ID_REG(8bit):
136 * PC_CC_REG(24bit):
151 * PC_CACHE_LSIZE_REG(8bit):
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| /freebsd/sys/contrib/dev/iwlwifi/ |
| H A D | iwl-context-info-gen3.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2018, 2020-2024 Intel Corporation
8 #include "iwl-context-info.h"
18 /* Set bit for enabling automatic function boot */
19 #define CSR_AUTO_FUNC_BOOT_ENA BIT(
178 struct iwl_prph_scratch_control control; global() member
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| /freebsd/sys/x86/include/ |
| H A D | x86_ieeefp.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
40 /* Deprecated historical FPU control interface */
61 FP_PS=0, /* 24 bit (single-precision) */
63 FP_PD, /* 53 bit (double-precision) */
64 FP_PE /* 64 bit (extended-precision) */
70 * Exception bit masks.
81 * FPU control word bit-field masks.
84 #define FP_PRC_FLD 0x300 /* precision control field */
85 #define FP_RND_FLD 0xc00 /* rounding control field */
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | sprd,pinctrl.txt | 5 The first block comprises some global control registers, and each
6 register contains several bit fields with one bit or several bits
8 pad driving level, system control select and so on ("domain pad
11 select 3.0v, then the pin can output 3.0v. "system control" is used
16 of them, so we can not make every Spreadtrum-special configuration
18 global configuration in future. Then we add one "sprd,control" to
19 set these various global control configuration, and we need use
22 Moreover we recognise every fields comprising one bit or several
23 bits in one global control registe
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDKernelCodeT.h | 1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
16 //---------------------------------------------------------------------------//
18 //---------------------------------------------------------------------------//
65 /// a number of bit fields. Every bit field has a mask (AMD_CODE_PROPERTY_*),
66 /// bit width (AMD_CODE_PROPERTY_*_WIDTH, and bit shift amount
69 /// (Note that bit fields cannot be used as their layout is
87 …BUFFER = ((1 << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH) - 1) << AMD_CODE_PROPE…
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| /freebsd/sys/dev/sound/pci/ |
| H A D | envy24.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
42 #define PCIR_LAC 0x40 /* Legacy Audio Control */
47 #define PCIM_LAC_IOADDR10 0x0020 /* I/O Address Alias Control */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
53 #define PCIR_LCC 0x42 /* Legacy Configuration Control */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
68 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */
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| /freebsd/share/man/man4/ |
| H A D | snd_emu10kx.4 | 2 .\" Copyright (c) 2003-2007 Yuriy Tsibizov
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
60 for details), and MPU401-compatible MIDI I/O controller, which is accessible
68 .Bl -bullet -compact
78 PCM support is limited to 48kHz/16 bit stereo (192kHz/24 bit part
83 to 48kHz/16 bit stereo (192kHz/24 bit part of this chipset is not supported).
94 .Bl -bullet -compact
96 Creative Sound Blaster Live!\& 24-Bit, identified by
104 .Qq Li "CA0106-DAT Audigy LS" .
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_pcie_w_reg.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
203 uint32_t control; member
376 * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically
377 * cleared after MSI-X message associated with this specific interrupt
378 * bit is sent (MSI-X acknowledge is received).
379 * - Software can set a bit in this register by writing 1 to the
380 * associated bit in the Interrupt Cause Set register
381 * Write-0 clears a bit. Write-1 has no effect.
382 * - On CPU Read - If clear_on_read control bit =TRUE, automatically
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| H A D | al_hal_pbs_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
163 /* [0xd8] Control */
165 /* [0xdc] Control */
167 /* [0xe0] Control */
169 /* [0xe4] Control */
171 /* [0xe8] Control */
173 /* [0xec] Control */
211 /* [0x138] Control */
213 /* [0x13c] Control */
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | analogix,anx7625.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Xin Ji <xji@analogixsemi.com>
14 The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
28 enable-gpios:
29 description: used for power on chip control, POWER_EN pin D2.
32 reset-gpios:
33 description: used for reset chip control, RESET_N pin B7.
36 vdd10-supply:
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| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | dscr.txt | 2 ------------------------------------
5 function for SoC control or status. Details vary considerably among from SoC
19 For device state control (enable/disable), each device control is assigned an
20 id which is used by individual device drivers to control the state as needed.
24 - compatible: must be "ti,c64x+dscr"
25 - reg: register area base and size
34 - ti,dscr-devstat
37 - ti,dscr-silicon-rev
38 offset, start bit, and bitsize of silicon revision field
40 - ti,dscr-rmii-resets
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| /freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
| H A D | config.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2019, 2023-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-201
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| /freebsd/sys/dev/e1000/ |
| H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
43 /* Wake Up Control */
50 /* Wake Up Filter Control */
67 /* Extended Device Control */
93 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
114 /* Receive Descriptor bit definitions */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
172 /* Management Control */
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| /freebsd/sys/amd64/vmm/amd/ |
| H A D | amdvi_priv.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #define BIT(n) (1ULL << (n)) macro
38 /* Return value of bits[n:m] where n and (n >= ) m are bit positions. */
40 ((1 << (((n) - (m)) + 1)) - 1))
45 #define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */
46 #define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */
47 #define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */
48 #define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */
49 #define AMDVI_PCI_CAP_EXT BIT(4) /* Miscellaneous information reg. */
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
18 bit lines from the automatic calibrated position.
19 Two set of 3-tuple setting for each (up to 3)
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | cs35l35.txt | 5 - compatible : "cirrus,cs35l35"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - interrupts : IRQ line info CS35L35.
14 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - cirrus,boost-ind-nanohenr
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| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | ti-syscon-reset.txt | 4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
6 typically provided by means of memory-mapped I/O registers. These registers are
22 ------
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| /freebsd/stand/common/ |
| H A D | isapnp.h | 16 * 4. Neither the name of the author nor the names of any co-contributors
61 state to compare one bit of the boards ID.
67 Bit[2] Reset CSN to 0
68 Bit[1] Return to the Wait for Key state
69 Bit[0] Reset all logical devices and restore configuration
70 registers to their power-up values.
72 A write to bit[0] of this register performs a reset function on
77 A write to bit[1] of this register causes all cards to enter the
81 A write to bit[2] of this register causes all cards to reset their
84 This register is write-only. The values are not sticky, that is,
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