Lines Matching +full:control +full:- +full:bit
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
42 #define PCIR_LAC 0x40 /* Legacy Audio Control */
47 #define PCIM_LAC_IOADDR10 0x0020 /* I/O Address Alias Control */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
53 #define PCIR_LCC 0x42 /* Legacy Configuration Control */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
68 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */
71 #define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */
72 #define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
74 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */
75 #define PCIM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
83 #define PCIM_I2S_16BIT 0x00 /* 16bit */
84 #define PCIM_I2S_18BIT 0x10 /* 18bit */
85 #define PCIM_I2S_20BIT 0x20 /* 20bit */
86 #define PCIM_I2S_24BIT 0x30 /* 24bit */
94 #define PCIR_POWER_STAT 0x84 /* Power Management Control and Status */
98 #define ENVY24_CCS_CTL 0x00 /* Control/Status Register */
100 #define ENVY24_CCS_CTL_DMAINT 0x40 /* DS DMA Channel-C interrupt */
101 #define ENVY24_CCS_CTL_DOSVOL 0x10 /* set the DOS WT volume control */
110 #define ENVY24_CCS_IMASK_PMT 0x10 /* Professional Multi-track */
120 #define ENVY24_CCS_ISTAT_PMT 0x10 /* Professional Multi-track */
146 #define ENVY24_CCS_AC97CMD_READY 0x08 /* AC'97 codec ready status bit */
179 #define ENVY24_CCS_I2CSTAT 0x13 /* I2C Port Control and Status Register */
198 #define ENVY24_CCI_PCTL 0x02 /* Playback Control Register */
204 #define ENVY24_CCI_PCTL_FLUSH 0x04 /* FIFO flush (sticky bit. Requires toggling) */
212 #define ENVY24_CCI_SOFTVOL 0x05 /* Soft Volume/Mute Control Register */
219 #define ENVY24_CCI_RCTL 0x12 /* Record Control Register */
230 #define ENVY24_CCI_GPIOCTL 0x22 /* GPIO Direction Control Register */
243 #define ENVY24_CCI_MTPDWN 0x31 /* Multi-Track Section Power Down Register */
247 #define ENVY24_CCI_MTPDWN_I2S 0x01 /* Multi-track I2S serial interface clock */
251 #define ENVY24_DDMA_ADDR0 0x00 /* DMA Base and Current Address bit 0-7 */
252 #define ENVY24_DDMA_ADDR8 0x01 /* DMA Base and Current Address bit 8-15 */
253 #define ENVY24_DDMA_ADDR16 0x02 /* DMA Base and Current Address bit 16-23 */
254 #define ENVY24_DDMA_ADDR24 0x03 /* DMA Base and Current Address bit 24-31 */
255 #define ENVY24_DDMA_CNT0 0x04 /* DMA Base and Current Count 0-7 */
256 #define ENVY24_DDMA_CNT8 0x05 /* DMA Base and Current Count 8-15 */
275 #define ENVY24_CS_CHIDX_CTL 0x04 /* Channel Control and Status register */
277 #define ENVY24_CS_CHIDX_VOL 0x06 /* Channel left and right volume/pan control */
278 /* Channel Control and Status Register at Index 4h */
284 #define ENVY24_CS_CTL_U8 0x04 /* 8-bit unsigned(or 16-bit signed) */
291 /* Professional Multi-Track Control Registers */
294 #define ENVY24_MT_INT_RMASK 0x80 /* Multi-track record interrupt mask */
295 #define ENVY24_MT_INT_PMASK 0x40 /* Multi-track playback interrupt mask */
296 #define ENVY24_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */
297 #define ENVY24_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */
328 #define ENVY24_MT_AC97CMD_RDY 0x08 /* AC'97 codec ready status bit */
329 #define ENVY24_MT_AC97CMD_ID 0x03 /* ID(0-3) for external AC 97 registers */
336 #define ENVY24_MT_PCTL 0x18 /* Playback and Record Control Register */
344 #define ENVY24_MT_RCTL 0x28 /* Record Control Register */
347 #define ENVY24_MT_PSDOUT 0x30 /* Routing Control Register for Data to PSDOUT[0:3] */
348 #define ENVY24_MT_SPDOUT 0x32 /* Routing Control Register for SPDOUT */
354 #define ENVY24_MT_VOLUME 0x38 /* Left/Right Volume Control Data Register */
358 #define ENVY24_MT_VOLIDX 0x3a /* Volume Control Stream Index Register */
359 #define ENVY24_MT_VOLRATE 0x3b /* Volume Control Rate Register */
360 #define ENVY24_MT_MONAC97 0x3c /* Digital Mixer Monitor Routing Control Register */
364 /* -------------------------------------------------------------------- */
370 used as master mixer, and it is able to control.
391 #define ENVY24_VOL_MIN 96 /* -144db(negate) */
394 /* -------------------------------------------------------------------- */
396 /* ENVY24 routing control defines */
398 ENVY24 has input->output data routing matrix switch. But original ENVY24
399 matrix control is so complex. So, in this driver, matrix control is
406 (NOTICE: this class is able to set only DAC-1 and S/PDIF output)
412 These parameters matrix is bit reduced from original ENVY24 matrix
437 /* -------------------------------------------------------------------- */
462 /* GPIO connect map of M-Audio Delta series */
472 /* M-Audio Delta series S/PDIF(CS84[01]4) control pin values */
478 /* M-Audio Delta series parameter */