Lines Matching +full:control +full:- +full:bit
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
43 /* Wake Up Control */
50 /* Wake Up Filter Control */
67 /* Extended Device Control */
93 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
114 /* Receive Descriptor bit definitions */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
171 /* Management Control */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
187 /* Receive Control */
217 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
256 /* Device Control */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
270 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
284 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
285 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
337 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
365 /* 1000/H is not supported, nor spec-compliant. */
378 /* LED Control */
392 /* Transmit Descriptor bit definitions */
415 /* Transmit Control */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
426 /* SerDes Control */
430 /* Receive Checksum Control */
478 /* Extended Configuration Control and Size */
496 /* Low Power IDLE Control */
536 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
537 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
538 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
540 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
561 /* If this bit asserted, the driver should claim the interrupt */
582 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
602 * Set/Read Register. Each bit is documented below:
673 /* Transmit Descriptor Control */
683 /* Flow Control Constants */
727 /* Loop limit on how long we wait for auto-negotiation to complete */
741 /* Flow Control */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
807 /* ETQF register bit definitions */
822 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
824 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
826 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
828 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
833 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
835 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
848 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
875 #define E1000_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */
891 /* PCI Express Control */
912 /* mPHY address control and data registers */
913 #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */
922 /* PHY Control Register */
962 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
974 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
986 /* 1000BASE-T Control Register */
987 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1002 /* 1000BASE-T Status Register */
1004 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
1014 /* PHY 1000 MII Register/Bit Definitions */
1016 #define PHY_CONTROL 0x00 /* Control Register */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1029 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1031 /* NVM Control */
1040 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1043 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1074 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1192 /* NVM Commands - Microwire */
1199 /* NVM Commands - SPI */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1258 /* Bit definitions for valid PHY IDs.
1290 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1295 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1301 /* M88E1000 PHY Specific Control Register */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1346 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1349 /* I347AT4 Extended PHY Specific Control Register */
1365 /* I347AT4 PHY Cable Diagnostics Control */
1378 /* BME1000 PHY Specific Control Register */
1382 * 15-5: page
1383 * 4-0: register offset
1396 /* MAC Specific Control Register */
1401 /* Page 193 - Port Control Registers */
1402 /* Kumeran Mode Control */
1406 /* Page 194 - KMRN Registers */
1409 /* MDI Control */
1421 /* SerDes Control */
1450 /* Tx Rate-Scheduler Config fields */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1498 /* Proxy Filter Control */
1513 /* VF Control */
1517 /* Lan ID bit field offset in status register */