1*c66ec88fSEmmanuel VadotDevice State Configuration Registers 2*c66ec88fSEmmanuel Vadot------------------------------------ 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotTI C6X SoCs contain a region of miscellaneous registers which provide various 5*c66ec88fSEmmanuel Vadotfunction for SoC control or status. Details vary considerably among from SoC 6*c66ec88fSEmmanuel Vadotto SoC with no two being alike. 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel VadotIn general, the Device State Configuration Registers (DSCR) will provide one or 9*c66ec88fSEmmanuel Vadotmore configuration registers often protected by a lock register where one or 10*c66ec88fSEmmanuel Vadotmore key values must be written to a lock register in order to unlock the 11*c66ec88fSEmmanuel Vadotconfiguration register for writes. These configuration register may be used to 12*c66ec88fSEmmanuel Vadotenable (and disable in some cases) SoC pin drivers, select peripheral clock 13*c66ec88fSEmmanuel Vadotsources (internal or pin), etc. In some cases, a configuration register is 14*c66ec88fSEmmanuel Vadotwrite once or the individual bits are write once. In addition to device config, 15*c66ec88fSEmmanuel Vadotthe DSCR block may provide registers which are used to reset peripherals, 16*c66ec88fSEmmanuel Vadotprovide device ID information, provide ethernet MAC addresses, as well as other 17*c66ec88fSEmmanuel Vadotmiscellaneous functions. 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel VadotFor device state control (enable/disable), each device control is assigned an 20*c66ec88fSEmmanuel Vadotid which is used by individual device drivers to control the state as needed. 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel VadotRequired properties: 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel Vadot- compatible: must be "ti,c64x+dscr" 25*c66ec88fSEmmanuel Vadot- reg: register area base and size 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel VadotOptional properties: 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadot NOTE: These are optional in that not all SoCs will have all properties. For 30*c66ec88fSEmmanuel Vadot SoCs which do support a given property, leaving the property out of the 31*c66ec88fSEmmanuel Vadot device tree will result in reduced functionality or possibly driver 32*c66ec88fSEmmanuel Vadot failure. 33*c66ec88fSEmmanuel Vadot 34*c66ec88fSEmmanuel Vadot- ti,dscr-devstat 35*c66ec88fSEmmanuel Vadot offset of the devstat register 36*c66ec88fSEmmanuel Vadot 37*c66ec88fSEmmanuel Vadot- ti,dscr-silicon-rev 38*c66ec88fSEmmanuel Vadot offset, start bit, and bitsize of silicon revision field 39*c66ec88fSEmmanuel Vadot 40*c66ec88fSEmmanuel Vadot- ti,dscr-rmii-resets 41*c66ec88fSEmmanuel Vadot offset and bitmask of RMII reset field. May have multiple tuples if more 42*c66ec88fSEmmanuel Vadot than one ethernet port is available. 43*c66ec88fSEmmanuel Vadot 44*c66ec88fSEmmanuel Vadot- ti,dscr-locked-regs 45*c66ec88fSEmmanuel Vadot possibly multiple tuples describing registers which are write protected by 46*c66ec88fSEmmanuel Vadot a lock register. Each tuple consists of the register offset, lock register 47*c66ec88fSEmmanuel Vadot offsset, and the key value used to unlock the register. 48*c66ec88fSEmmanuel Vadot 49*c66ec88fSEmmanuel Vadot- ti,dscr-kick-regs 50*c66ec88fSEmmanuel Vadot offset and key values of two "kick" registers used to write protect other 51*c66ec88fSEmmanuel Vadot registers in DSCR. On SoCs using kick registers, the first key must be 52*c66ec88fSEmmanuel Vadot written to the first kick register and the second key must be written to 53*c66ec88fSEmmanuel Vadot the second register before other registers in the area are write-enabled. 54*c66ec88fSEmmanuel Vadot 55*c66ec88fSEmmanuel Vadot- ti,dscr-mac-fuse-regs 56*c66ec88fSEmmanuel Vadot MAC addresses are contained in two registers. Each element of a MAC address 57*c66ec88fSEmmanuel Vadot is contained in a single byte. This property has two tuples. Each tuple has 58*c66ec88fSEmmanuel Vadot a register offset and four cells representing bytes in the register from 59*c66ec88fSEmmanuel Vadot most significant to least. The value of these four cells is the MAC byte 60*c66ec88fSEmmanuel Vadot index (1-6) of the byte within the register. A value of 0 means the byte 61*c66ec88fSEmmanuel Vadot is unused in the MAC address. 62*c66ec88fSEmmanuel Vadot 63*c66ec88fSEmmanuel Vadot- ti,dscr-devstate-ctl-regs 64*c66ec88fSEmmanuel Vadot This property describes the bitfields used to control the state of devices. 65*c66ec88fSEmmanuel Vadot Each tuple describes a range of identical bitfields used to control one or 66*c66ec88fSEmmanuel Vadot more devices (one bitfield per device). The layout of each tuple is: 67*c66ec88fSEmmanuel Vadot 68*c66ec88fSEmmanuel Vadot start_id num_ids reg enable disable start_bit nbits 69*c66ec88fSEmmanuel Vadot 70*c66ec88fSEmmanuel Vadot Where: 71*c66ec88fSEmmanuel Vadot start_id is device id for the first device control in the range 72*c66ec88fSEmmanuel Vadot num_ids is the number of device controls in the range 73*c66ec88fSEmmanuel Vadot reg is the offset of the register holding the control bits 74*c66ec88fSEmmanuel Vadot enable is the value to enable a device 75*c66ec88fSEmmanuel Vadot disable is the value to disable a device (0xffffffff if cannot disable) 76*c66ec88fSEmmanuel Vadot start_bit is the bit number of the first bit in the range 77*c66ec88fSEmmanuel Vadot nbits is the number of bits per device control 78*c66ec88fSEmmanuel Vadot 79*c66ec88fSEmmanuel Vadot- ti,dscr-devstate-stat-regs 80*c66ec88fSEmmanuel Vadot This property describes the bitfields used to provide device state status 81*c66ec88fSEmmanuel Vadot for device states controlled by the DSCR. Each tuple describes a range of 82*c66ec88fSEmmanuel Vadot identical bitfields used to provide status for one or more devices (one 83*c66ec88fSEmmanuel Vadot bitfield per device). The layout of each tuple is: 84*c66ec88fSEmmanuel Vadot 85*c66ec88fSEmmanuel Vadot start_id num_ids reg enable disable start_bit nbits 86*c66ec88fSEmmanuel Vadot 87*c66ec88fSEmmanuel Vadot Where: 88*c66ec88fSEmmanuel Vadot start_id is device id for the first device status in the range 89*c66ec88fSEmmanuel Vadot num_ids is the number of devices covered by the range 90*c66ec88fSEmmanuel Vadot reg is the offset of the register holding the status bits 91*c66ec88fSEmmanuel Vadot enable is the value indicating device is enabled 92*c66ec88fSEmmanuel Vadot disable is the value indicating device is disabled 93*c66ec88fSEmmanuel Vadot start_bit is the bit number of the first bit in the range 94*c66ec88fSEmmanuel Vadot nbits is the number of bits per device status 95*c66ec88fSEmmanuel Vadot 96*c66ec88fSEmmanuel Vadot- ti,dscr-privperm 97*c66ec88fSEmmanuel Vadot Offset and default value for register used to set access privilege for 98*c66ec88fSEmmanuel Vadot some SoC devices. 99*c66ec88fSEmmanuel Vadot 100*c66ec88fSEmmanuel Vadot 101*c66ec88fSEmmanuel VadotExample: 102*c66ec88fSEmmanuel Vadot 103*c66ec88fSEmmanuel Vadot device-state-config-regs@2a80000 { 104*c66ec88fSEmmanuel Vadot compatible = "ti,c64x+dscr"; 105*c66ec88fSEmmanuel Vadot reg = <0x02a80000 0x41000>; 106*c66ec88fSEmmanuel Vadot 107*c66ec88fSEmmanuel Vadot ti,dscr-devstat = <0>; 108*c66ec88fSEmmanuel Vadot ti,dscr-silicon-rev = <8 28 0xf>; 109*c66ec88fSEmmanuel Vadot ti,dscr-rmii-resets = <0x40020 0x00040000>; 110*c66ec88fSEmmanuel Vadot 111*c66ec88fSEmmanuel Vadot ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>; 112*c66ec88fSEmmanuel Vadot ti,dscr-devstate-ctl-regs = 113*c66ec88fSEmmanuel Vadot <0 12 0x40008 1 0 0 2 114*c66ec88fSEmmanuel Vadot 12 1 0x40008 3 0 30 2 115*c66ec88fSEmmanuel Vadot 13 2 0x4002c 1 0xffffffff 0 1>; 116*c66ec88fSEmmanuel Vadot ti,dscr-devstate-stat-regs = 117*c66ec88fSEmmanuel Vadot <0 10 0x40014 1 0 0 3 118*c66ec88fSEmmanuel Vadot 10 2 0x40018 1 0 0 3>; 119*c66ec88fSEmmanuel Vadot 120*c66ec88fSEmmanuel Vadot ti,dscr-mac-fuse-regs = <0x700 1 2 3 4 121*c66ec88fSEmmanuel Vadot 0x704 5 6 0 0>; 122*c66ec88fSEmmanuel Vadot 123*c66ec88fSEmmanuel Vadot ti,dscr-privperm = <0x41c 0xaaaaaaaa>; 124*c66ec88fSEmmanuel Vadot 125*c66ec88fSEmmanuel Vadot ti,dscr-kick-regs = <0x38 0x83E70B13 126*c66ec88fSEmmanuel Vadot 0x3c 0x95A4F1E0>; 127*c66ec88fSEmmanuel Vadot }; 128