Lines Matching +full:control +full:- +full:bit

16  * 4. Neither the name of the author nor the names of any co-contributors
61 state to compare one bit of the boards ID.
67 Bit[2] Reset CSN to 0
68 Bit[1] Return to the Wait for Key state
69 Bit[0] Reset all logical devices and restore configuration
70 registers to their power-up values.
72 A write to bit[0] of this register performs a reset function on
77 A write to bit[1] of this register causes all cards to enter the
81 A write to bit[2] of this register causes all cards to reset their
84 This register is write-only. The values are not sticky, that is,
95 pointer to the byte-serial device is reset. This register is
102 The Status register must be polled until bit[0] is set before this
108 Bit[0] when set indicates it is okay to read the next data byte
127 device, this location should be a read-only value of 0x00.
130 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
131 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
136 whether or not the logical device is active on the ISA bus. Bit[0],
147 Bit[7:2] Reserved and must return 0 on reads
148 Bit[1] Enable I/O Range check, if set then I/O Range Check
152 Bit[0], if set, forces the logical device to respond to I/O reads
158 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
159 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
168 Offset 2: Memory control
169 Bit[1] specifies 8/16-bit control. This bit is set to indicate
170 16-bit memory, and cleared to indicate 8-bit memory.
171 Bit[0], if cleared, indicates the next field can be used as a range
174 Bit[0], if set, indicates the next field is the upper limit for
175 the address. - - Bit[0] is read-only.
178 Offset 5-Offset 7: filler, unused.
192 Offset 1: Bit[1]: level(1:hi, 0:low),
193 Bit[0]: type (1:level, 0:edge)
205 /*** 32-bit memory accesses are at 0x76 ***/
223 #define SM_RES_RESERVED 0xa-0xd
234 #define LG_RES_RESERVED 0x7-0x7f
246 u_long flags; /* OS-reserved flags */
257 int control; /* Memory Control Register */ member