Home
last modified time | relevance | path

Searched +full:altera +full:- +full:www (Results 1 – 25 of 28) sorted by relevance

12

/linux/Documentation/networking/device_drivers/ethernet/altera/
H A Daltera_tse.rst1 .. SPDX-License-Identifier: GPL-2.0
6 Altera Triple-Speed Ethernet MAC driver
9 Copyright |copy| 2008-2014 Altera Corporation
11 This is the driver for the Altera Triple-Speed Ethernet (TSE) controllers
19 For more information visit www.altera.com and www.rocketboards.org. Support
20 forums for the driver may be found on www.rocketboards.org, and a design used
24 The Triple-Speed Ethernet, SGDMA, and MSGDMA components are all soft IP
25 components that can be assembled and built into an FPGA using the Altera
31 Triple-Speed Ethernet instance is using an SGDMA or MSGDMA component. The
36 The SGDMA component is to be deprecated in the near future (over the next 1-2
[all …]
/linux/Documentation/arch/nios2/
H A Dnios2.rst10 http://www.rocketboards.org/foswiki/Documentation/NiosIILinuxUserManual
13 http://www.altera.com/literature/lit-nio2.jsp
17 Nios II is a 32-bit embedded-processor architecture designed specifically for the
18 Altera family of FPGAs. In order to support Linux, Nios II needs to be configured
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_vt.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
6 /dts-v1/;
10 model = "Altera SOCFPGA VT";
11 compatible = "altr,socfpga-vt", "altr,socfpga";
27 clock-frequency = <10000000>;
33 broken-cd;
34 bus-width = <4>;
35 cap-mmc-highspeed;
36 cap-sd-highspeed;
[all …]
H A Dsocfpga_arria10_socdk_sdmmc.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
6 /dts-v1/;
11 cap-sd-highspeed;
12 cap-mmc-highspeed;
13 broken-cd;
14 bus-width = <4>;
15 clk-phase-sd-hs = <0>, <135>;
19 sdmmca-ecc@ff8c2c00 {
20 compatible = "altr,socfpga-sdmmc-ecc";
[all …]
H A Dsocfpga_arria5.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_cyclone5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_arria5_socdk.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
9 model = "Altera SOCFPGA Arria V SoC Development Kit";
10 compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";
14 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
32 led-hps0 {
37 led-hps1 {
42 led-hps2 {
47 led-hps3 {
[all …]
H A Dsocfpga_arria10_socdk.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Altera Corporation <www.altera.com>
8 model = "Altera SOCFPGA Arria 10";
9 compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
31 label = "a10sr-led0";
36 label = "a10sr-led1";
41 label = "a10sr-led2";
46 label = "a10sr-led3";
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Altera <www.altera.com>
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
[all …]
/linux/drivers/clk/socfpga/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
12 CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init);
13 CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init);
14 CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init);
15 CLK_OF_DECLARE(socfpga_a10_pll_clk, "altr,socfpga-a10-pll-clock",
17 CLK_OF_DECLARE(socfpga_a10_perip_clk, "altr,socfpga-a10-perip-clk",
19 CLK_OF_DECLARE(socfpga_a10_gate_clk, "altr,socfpga-a10-gate-clk",
H A Dclk-periph.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
23 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()
24 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()
26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
28 val &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()
[all …]
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
79 const char *clk_name = node->name; in __socfpga_pll_init()
91 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); in __socfpga_pll_init()
95 pll_clk->hw.reg = clk_mgr_base_addr + reg; in __socfpga_pll_init()
[all …]
H A Dclk-gate.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
94 if (socfpgaclk->fixed_div) in socfpga_clk_get_div()
95 div = socfpgaclk->fixed_div; in socfpga_clk_get_div()
96 else if (socfpgaclk->div_reg) { in socfpga_clk_get_div()
97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_get_div()
98 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_clk_get_div()
[all …]
/linux/arch/nios2/include/asm/
H A Dkgdb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015 Altera Corporation
6 * Based on the code posted by Kazuyasu on the Altera Forum at:
7 * http://www.alteraforum.com/forum/showpost.php?p=77003&postcount=20
/linux/arch/nios2/include/uapi/asm/
H A Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2013 Altera Corporation
15 * this program. If not, see <http://www.gnu.org/licenses/>.
H A Dsignal.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright Altera Corporation (C) 2013. All rights reserved
15 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <asm-generic/signal.h>
/linux/arch/nios2/kernel/
H A Dkgdb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2015 Altera Corporation
8 * Based on the code posted by Kazuyasu on the Altera Forum at:
9 * http://www.alteraforum.com/forum/showpost.php?p=77003&postcount=20
20 { "zero", GDB_SIZEOF_REG, -1 },
36 { "r16", GDB_SIZEOF_REG, -1 },
37 { "r17", GDB_SIZEOF_REG, -1 },
38 { "r18", GDB_SIZEOF_REG, -1 },
39 { "r19", GDB_SIZEOF_REG, -1 },
40 { "r20", GDB_SIZEOF_REG, -1 },
[all …]
H A Dentry.S4 * Copyright (C) 2013-2014 Altera Corporation
9 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
12 * Copyright (C) 2000 Lineo Inc. (www.lineo.com)
29 #include <asm/asm-offsets.h>
30 #include <asm/asm-macros.h>
40 andhi \reg, sp, %hi(~(THREAD_SIZE-1))
42 addi \reg, r0, %lo(~(THREAD_SIZE-1))
51 * ea-4 = address of interrupted insn (ea must be preserved).
58 movui et, (KUSER_BASE + 4 + (cmpxchg_stw - __kuser_helper_start))
61 subi et, et, (cmpxchg_stw - cmpxchg_ldw) /* et = cmpxchg_ldw + 4 */
[all …]
/linux/drivers/tty/serial/8250/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
15 here are those that are setting up dedicated Ethernet WWW/FTP
23 non-standard serial ports, since the configuration information will
51 If you did not notice yet and/or you have userspace from pre-3.7, it
146 Note that serial ports on NetMos 9835 Multi-I/O cards are handled
169 Say Y here to enable support for 16-bit PCMCIA serial devices,
171 multi-function Ethernet/modem cards. (PCMCIA- or PC-cards are
172 credit-card size devices often used with laptops.)
198 PCI enumeration and any ports that may be added at run-time
199 via hot-plug, or any ISA multi-port serial cards.
[all …]
/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
[all …]
/linux/drivers/i2c/busses/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
73 will be called i2c-amd8111.
83 be called i2c-amd-mp2-pci and i2c-amd-mp2-plat.
[all …]
/linux/arch/arc/boot/dts/
H A Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
[all …]
/linux/drivers/usb/serial/
H A Dftdi_sio_ids.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Philipp Gühring - pg@futureware.at - added the Device ID of the USB relais
25 #define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */
26 #define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */
27 #define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */
28 #define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */
29 #define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */
30 #define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */
31 #define FTDI_FT4232HP_PID 0x6043 /* Quad channel hi-speed device with PD */
32 #define FTDI_FT233HP_PID 0x6044 /* Dual channel hi-speed device with PD */
[all …]
/linux/drivers/comedi/drivers/
H A Damplc_dio200_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
[all …]
/linux/
H A DCREDITS1 This is at least a partial credits-file of people that have
4 scripts. The fields are: name (N), email (E), web-address
6 snail-mail address (S).
10 ----------
29 W: http://www.arbornet.org/~dragos
49 W: http://www.csn.ul.ie/~airlied
51 D: in-kernel DRM Maintainer
57 W: http://www.moses.uklinux.net/patches
65 W: https://www.almesberger.net/
76 E: tim_alpaerts@toyota-motor-europe.com
[all …]

12