1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2012 Altera Corporation <www.altera.com> 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring/dts-v1/; 7*724ba675SRob Herring/* First 4KB has trampoline code for secondary cores. */ 8*724ba675SRob Herring/memreserve/ 0x00000000 0x0001000; 9*724ba675SRob Herring#include "socfpga.dtsi" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring soc { 13*724ba675SRob Herring clkmgr@ffd04000 { 14*724ba675SRob Herring clocks { 15*724ba675SRob Herring osc1 { 16*724ba675SRob Herring clock-frequency = <25000000>; 17*724ba675SRob Herring }; 18*724ba675SRob Herring }; 19*724ba675SRob Herring }; 20*724ba675SRob Herring 21*724ba675SRob Herring mmc0: mmc@ff704000 { 22*724ba675SRob Herring broken-cd; 23*724ba675SRob Herring bus-width = <4>; 24*724ba675SRob Herring cap-mmc-highspeed; 25*724ba675SRob Herring cap-sd-highspeed; 26*724ba675SRob Herring clk-phase-sd-hs = <0>, <135>; 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring sysmgr@ffd08000 { 30*724ba675SRob Herring cpu1-start-addr = <0xffd080c4>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring }; 33*724ba675SRob Herring}; 34*724ba675SRob Herring 35*724ba675SRob Herring&watchdog0 { 36*724ba675SRob Herring status = "okay"; 37*724ba675SRob Herring}; 38