Lines Matching +full:altera +full:- +full:www

1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
94 if (socfpgaclk->fixed_div) in socfpga_clk_get_div()
95 div = socfpgaclk->fixed_div; in socfpga_clk_get_div()
96 else if (socfpgaclk->div_reg) { in socfpga_clk_get_div()
97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_get_div()
98 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_clk_get_div()
100 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_get_div()
125 req->rate = req->best_parent_rate / div; in socfpga_clk_determine_rate()
144 const char *clk_name = node->name; in socfpga_gate_init()
158 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); in socfpga_gate_init()
163 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; in socfpga_gate_init()
164 socfpga_clk->hw.bit_idx = clk_gate[1]; in socfpga_gate_init()
166 ops->enable = clk_gate_ops.enable; in socfpga_gate_init()
167 ops->disable = clk_gate_ops.disable; in socfpga_gate_init()
170 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); in socfpga_gate_init()
172 socfpga_clk->fixed_div = 0; in socfpga_gate_init()
174 socfpga_clk->fixed_div = fixed_div; in socfpga_gate_init()
176 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in socfpga_gate_init()
178 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in socfpga_gate_init()
179 socfpga_clk->shift = div_reg[1]; in socfpga_gate_init()
180 socfpga_clk->width = div_reg[2]; in socfpga_gate_init()
182 socfpga_clk->div_reg = NULL; in socfpga_gate_init()
185 of_property_read_string(node, "clock-output-names", &clk_name); in socfpga_gate_init()
193 ops->get_parent = NULL; in socfpga_gate_init()
194 ops->set_parent = NULL; in socfpga_gate_init()
198 socfpga_clk->hw.hw.init = &init; in socfpga_gate_init()
200 hw_clk = &socfpga_clk->hw.hw; in socfpga_gate_init()