Lines Matching +full:altera +full:- +full:www

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  *  Copyright 2011-2012 Calxeda, Inc.
4  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6  * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
23 	if (socfpgaclk->fixed_div) {  in clk_periclk_recalc_rate()
24 		div = socfpgaclk->fixed_div;  in clk_periclk_recalc_rate()
26 		if (socfpgaclk->div_reg) {  in clk_periclk_recalc_rate()
27 			val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in clk_periclk_recalc_rate()
28 			val &= GENMASK(socfpgaclk->width - 1, 0);  in clk_periclk_recalc_rate()
31 		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);  in clk_periclk_recalc_rate()
56 	const char *clk_name = node->name;  in __socfpga_periph_init()
69 	periph_clk->hw.reg = clk_mgr_base_addr + reg;  in __socfpga_periph_init()
71 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);  in __socfpga_periph_init()
73 		periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];  in __socfpga_periph_init()
74 		periph_clk->shift = div_reg[1];  in __socfpga_periph_init()
75 		periph_clk->width = div_reg[2];  in __socfpga_periph_init()
77 		periph_clk->div_reg = NULL;  in __socfpga_periph_init()
80 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);  in __socfpga_periph_init()
82 		periph_clk->fixed_div = 0;  in __socfpga_periph_init()
84 		periph_clk->fixed_div = fixed_div;  in __socfpga_periph_init()
86 	of_property_read_string(node, "clock-output-names", &clk_name);  in __socfpga_periph_init()
96 	periph_clk->hw.hw.init = &init;  in __socfpga_periph_init()
97 	hw_clk = &periph_clk->hw.hw;  in __socfpga_periph_init()