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/freebsd/sys/dev/gve/
H A Dgve_rx_dqo.c36 gve_free_rx_mbufs_dqo(struct gve_rx_ring *rx) in gve_free_rx_mbufs_dqo() argument
41 if (gve_is_qpl(rx->com.priv)) in gve_free_rx_mbufs_dqo()
44 for (i = 0; i < rx->dqo.buf_cnt; i++) { in gve_free_rx_mbufs_dqo()
45 buf = &rx->dqo.bufs[i]; in gve_free_rx_mbufs_dqo()
49 bus_dmamap_sync(rx->dqo.buf_dmatag, buf->dmamap, in gve_free_rx_mbufs_dqo()
51 bus_dmamap_unload(rx->dqo.buf_dmatag, buf->dmamap); in gve_free_rx_mbufs_dqo()
60 struct gve_rx_ring *rx = &priv->rx[i]; in gve_rx_free_ring_dqo() local
63 if (rx->dqo.compl_ring != NULL) { in gve_rx_free_ring_dqo()
64 gve_dma_free_coherent(&rx->dqo.compl_ring_mem); in gve_rx_free_ring_dqo()
65 rx->dqo.compl_ring = NULL; in gve_rx_free_ring_dqo()
[all …]
H A Dgve_rx.c38 struct gve_rx_ring *rx = &priv->rx[i]; in gve_rx_free_ring_gqi() local
40 if (rx->page_info != NULL) { in gve_rx_free_ring_gqi()
41 free(rx->page_info, M_GVE); in gve_rx_free_ring_gqi()
42 rx->page_info = NULL; in gve_rx_free_ring_gqi()
45 if (rx->data_ring != NULL) { in gve_rx_free_ring_gqi()
46 gve_dma_free_coherent(&rx->data_ring_mem); in gve_rx_free_ring_gqi()
47 rx->data_ring = NULL; in gve_rx_free_ring_gqi()
50 if (rx->desc_ring != NULL) { in gve_rx_free_ring_gqi()
51 gve_dma_free_coherent(&rx->desc_ring_mem); in gve_rx_free_ring_gqi()
52 rx->desc_ring = NULL; in gve_rx_free_ring_gqi()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td28 (outs mGPR:$rz), (ins mGPR:$rx, mGPR:$ry), !strconcat(opstr, "\t$rz, $rx, $ry"),
29 [(set mGPR:$rz, (opnode mGPR:$rx, mGPR:$ry)) ]> {
31 bits<3> rx;
34 let Inst{10 - 8} = rx;
41 AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rZ, sGPR:$rx), !strconcat(opstr, "\t$rz, $rx"),
42 [(set sGPR:$rz, (opnode sGPR:$rZ, sGPR:$rx))]> {
44 bits<4> rx;
48 let Inst{5 - 2} = rx;
54 AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rZ, sGPR:$rx), !strconcat(opstr, "\t$rz, $rx"),
57 bits<4> rx;
[all …]
H A DCSKYInstrFormats.td77 // Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
82 !strconcat(op, "\t$rz, $rx, $imm16"), pattern> {
84 bits<5> rx;
87 let Inst{20 - 16} = rx;
129 // Format< OP[6] | SOP[5] | RX[5] | 0000000000000000[16] >
132 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
133 !strconcat(op, "\t$rx"), pattern> {
134 bits<5> rx;
137 let Inst{20 - 16} = rx;
[all …]
H A DCSKYInstrInfo.td528 [(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
533 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
534 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
536 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
537 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
539 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
540 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
542 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
543 [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
545 def ROTRI32 : CSKYPseudo<(outs GPR:$rz), (ins GPR:$rx, oimm
[all...]
H A DCSKYInstrFormatsF1.td42 bits<5> rx;
45 let Inst{20 - 16} = {rx};
56 : F_XZ_FG<3, sop, (outs regtype1:$vrz), (ins regtype2:$rx), !strconcat(op, "\t$vrz, $rx"),
144 bits<5> rx;
149 let Inst{20 - 16} = rx; //rx
159 bits<5> rx;
163 let Inst{20 - 16} = rx; //rx
176 let Inst{20 - 16} = 0; //rx
185 bits<5> rx;
191 let Inst{20 - 16} = rx; // rx;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp70 void ExecutionDomainFix::setLiveReg(int rx, DomainValue *dv) { in setLiveReg() argument
71 assert(unsigned(rx) < NumRegs && "Invalid index"); in setLiveReg()
74 if (LiveRegs[rx] == dv) in setLiveReg()
76 if (LiveRegs[rx]) in setLiveReg()
77 release(LiveRegs[rx]); in setLiveReg()
78 LiveRegs[rx] = retain(dv); in setLiveReg()
81 void ExecutionDomainFix::kill(int rx) { in kill() argument
82 assert(unsigned(rx) < NumRegs && "Invalid index"); in kill()
84 if (!LiveRegs[rx]) in kill()
87 release(LiveRegs[rx]); in kill()
[all …]
/freebsd/sys/net80211/
H A Dieee80211_ioctl.h42 uint32_t ns_rx_data; /* rx data frames */
43 uint32_t ns_rx_mgmt; /* rx management frames */
44 uint32_t ns_rx_ctrl; /* rx control frames */
45 uint32_t ns_rx_ucast; /* rx unicast frames */
46 uint32_t ns_rx_mcast; /* rx multi/broadcast frames */
47 uint64_t ns_rx_bytes; /* rx data count (bytes) */
48 uint64_t ns_rx_beacons; /* rx beacon frames */
49 uint32_t ns_rx_proberesp; /* rx probe response frames */
51 uint32_t ns_rx_dup; /* rx discard 'cuz dup */
52 uint32_t ns_rx_noprivacy; /* rx w/ wep but privacy off */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.td82 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm8),
87 FRI16_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
91 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm8, i32imm:$size),
92 !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin>;
96 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm8),
101 FRI16R_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
105 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm8),
106 !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin> {
107 let Constraints = "$rx_ = $rx";
112 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm8),
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_port.h150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
160 uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2055.h38 #define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */
39 #define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */
40 #define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */
41 #define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */
133 #define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */
134 #define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */
135 #define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */
136 #define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */
137 #define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */
138 #define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */
[all …]
/freebsd/sys/dev/cas/
H A Dif_casreg.h73 #define CAS_CAW_RX_WGHT_MASK 0x00000003 /* RX DMA factor for... */
75 #define CAS_CAW_TX_WGHT_MASK 0x0000000c /* RX DMA factor for... */
91 #define CAS_INTR_RX_DONE 0x00000010 /* >=1 RX frames transferred. */
92 #define CAS_INTR_RX_BUF_NA 0x00000020 /* RX buffer not available */
93 #define CAS_INTR_RX_TAG_ERR 0x00000040 /* RX FIFO tag corrupted. */
94 #define CAS_INTR_RX_COMP_FULL 0x00000080 /* RX completion ring full */
95 #define CAS_INTR_RX_BUF_AEMPTY 0x00000100 /* RX desc. ring almost empty */
96 #define CAS_INTR_RX_COMP_AFULL 0x00000200 /* RX cmpl. ring almost full */
101 #define CAS_INTR_RX_MAC_INT 0x00008000 /* RX MAC interrupt */
130 #define CAS_RESET_RX 0x00000002 /* Reset RX DMA engine. */
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_gen.h106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
130 /* [0x10] RX VMPR control */
132 /* [0x14] RX VMPR Buffer2 MSB address */
134 /* [0x18] RX queue Target-ID values */
136 /* [0x1c] RX queue BUF1 Target-ID values */
138 /* [0x20] RX queue BUF2 Target-ID values */
140 /* [0x24] RX queue Direct Data Placement Target-ID values */
[all …]
/freebsd/sys/dev/e1000/
H A De1000_regs.h88 #define E1000_RCTL 0x00100 /* Rx Control - RW */
91 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
148 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
152 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
153 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
154 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
155 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
156 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
157 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
159 /* Split and Replication Rx Control - RW */
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_calib.c66 r88e_iq_calib_chain(struct rtwn_softc *sc, uint16_t tx[2], uint16_t rx[2]) in r88e_iq_calib_chain()
70 /* Set Rx IQ calibration mode table. */ in r88e_iq_calib_chain()
113 /* Set Rx IQ calibration mode table. */ in r88e_iq_calib_chain()
143 return (1); /* Rx failed. */ in r88e_iq_calib_chain()
145 /* Read Rx IQ calibration results. */ in r88e_iq_calib_chain()
146 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(0)), in r88e_iq_calib_chain()
148 rx[1] = MS(status, R92C_POWER_IQK_RESULT); in r88e_iq_calib_chain()
149 if (rx[0] == 0x132 || rx[1] == 0x036) in r88e_iq_calib_chain()
150 return (1); /* Rx failed. */ in r88e_iq_calib_chain()
152 return (3); /* Both Tx and Rx succeeded. */ in r88e_iq_calib_chain()
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_calib.c72 uint16_t rx[2]) in r92ce_iq_calib_chain()
121 return (1); /* Rx failed. */ in r92ce_iq_calib_chain()
122 /* Read Rx IQ calibration results. */ in r92ce_iq_calib_chain()
123 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)), in r92ce_iq_calib_chain()
125 rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)), in r92ce_iq_calib_chain()
127 if (rx[0] == 0x132 || rx[1] == 0x036) in r92ce_iq_calib_chain()
128 return (1); /* Rx failed. */ in r92ce_iq_calib_chain()
130 return (3); /* Both Tx and Rx succeeded. */ in r92ce_iq_calib_chain()
135 uint16_t rx[2][2], struct r92ce_iq_cal_reg_vals *vals) in r92ce_iq_calib_run()
226 tx[chain], rx[chain]); in r92ce_iq_calib_run()
[all …]
/freebsd/sys/dev/igc/
H A Digc_regs.h34 #define IGC_RCTL 0x00100 /* Rx Control - RW */
37 #define IGC_RXCW 0x00180 /* Rx Configuration Word - RO */
67 #define IGC_ERT 0x02008 /* Early Rx Threshold - RW */
71 #define IGC_RDFH 0x02410 /* Rx Data FIFO Head - RW */
72 #define IGC_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
73 #define IGC_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
74 #define IGC_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
75 #define IGC_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
76 #define IGC_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
78 /* Split and Replication Rx Control - RW */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dqcom,lpass-rx-macro.yaml4 $id: http://devicetree.org/schemas/sound/qcom,lpass-rx-macro.yaml#
7 title: LPASS(Low Power Audio Subsystem) RX Macro audio codec
16 - qcom,sc7280-lpass-rx-macro
17 - qcom,sm8250-lpass-rx-macro
18 - qcom,sm8450-lpass-rx-macro
19 - qcom,sm8550-lpass-rx-macro
20 - qcom,sc8280xp-lpass-rx-macro
23 - qcom,sm8650-lpass-rx-macro
24 - qcom,x1e80100-lpass-rx-macro
25 - const: qcom,sm8550-lpass-rx
[all...]
/freebsd/sys/dev/mlx5/mlx5_accel/
H A Dmlx5_ipsec_fs.c73 * Rx Tables and rules: +=========+
84 * +--------------->---------------------------------------------------->| RX NS |
528 struct mlx5e_ipsec_rx *rx; in rx_add_rule() local
532 rx = (attrs->family == AF_INET) ? ipsec->rx_ipv4 : ipsec->rx_ipv6; in rx_add_rule()
569 dest[0].ft = rx->ft.status; in rx_add_rule()
589 rule = mlx5_add_flow_rules(rx->ft.sa, spec, &flow_act, dest, 2); in rx_add_rule()
592 mlx5_core_err(mdev, "fail to add RX ipsec rule err=%d\n", err); in rx_add_rule()
601 rule = mlx5_add_flow_rules(rx->ft.sa, spec, &flow_act, dest, 2); in rx_add_rule()
605 "fail to add RX ipsec zero vid rule err=%d\n", in rx_add_rule()
1361 struct mlx5e_ipsec_rx *rx; in rx_add_policy() local
[all …]
/freebsd/tools/tools/net80211/wlanstats/
H A Dwlanstats.c66 { 5, "rx_badversion", "bvers", "rx frame with bad version" },
68 { 5, "rx_tooshort", "2short", "rx frame too short" },
70 { 5, "rx_wrongbss", "wrbss", "rx from wrong bssid" },
72 { 5, "rx_dup", "rxdup", "rx discard 'cuz dup" },
74 { 5, "rx_wrongdir", "wrdir", "rx w/ wrong direction" },
76 { 5, "rx_mcastecho", "mecho", "rx discard 'cuz mcast echo" },
78 { 6, "rx_notassoc", "!assoc", "rx discard 'cuz sta !assoc" },
80 { 6, "rx_noprivacy", "nopriv", "rx w/ wep but privacy off" },
82 { 6, "rx_unencrypted", "unencr", "rx w/o wep and privacy on" },
84 { 7, "rx_wepfail", "wepfail", "rx wep processing failed" },
[all …]
/freebsd/sys/dev/wtap/
H A Dif_wtapioctl.h58 u_int32_t ast_rxorn; /* rx overrun interrupts */
59 u_int32_t ast_rxeol; /* rx eol interrupts */
88 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
89 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
90 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
91 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
92 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
93 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
94 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
95 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos.c328 sc->rx.desc_ring[index].des0 = htole32((uint32_t)paddr); in eqos_setup_rxdesc()
329 sc->rx.desc_ring[index].des1 = htole32((uint32_t)(paddr >> 32)); in eqos_setup_rxdesc()
330 sc->rx.desc_ring[index].des2 = htole32(0); in eqos_setup_rxdesc()
331 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, BUS_DMASYNC_PREWRITE); in eqos_setup_rxdesc()
332 sc->rx.desc_ring[index].des3 = htole32(EQOS_RDES3_OWN | EQOS_RDES3_IOC | in eqos_setup_rxdesc()
344 error = bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, in eqos_setup_rxbuf()
345 sc->rx.buf_map[index].map, m, &seg, &nsegs, 0); in eqos_setup_rxbuf()
349 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, in eqos_setup_rxbuf()
352 sc->rx.buf_map[index].mbuf = m; in eqos_setup_rxbuf()
479 (uint32_t)(sc->rx.desc_ring_paddr >> 32)); in eqos_init_rings()
[all …]
/freebsd/sys/dev/vge/
H A Dif_vgereg.h54 #define VGE_RXCTL 0x06 /* RX control register */
82 #define VGE_RXHOSTERR 0x23 /* RX host error status */
87 #define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */
89 #define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */
90 #define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
91 #define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */
93 #define VGE_RXQTIMER 0x3F /* RX queue timer pend register */
98 #define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */
105 #define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */
127 #define VGE_RXCFG 0x7E /* MAC RX config */
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_calib.c72 uint16_t rx[2]) in r92c_iq_calib_chain()
121 return (1); /* Rx failed. */ in r92c_iq_calib_chain()
122 /* Read Rx IQ calibration results. */ in r92c_iq_calib_chain()
123 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)), in r92c_iq_calib_chain()
125 rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)), in r92c_iq_calib_chain()
127 if (rx[0] == 0x132 || rx[1] == 0x036) in r92c_iq_calib_chain()
128 return (1); /* Rx failed. */ in r92c_iq_calib_chain()
130 return (3); /* Both Tx and Rx succeeded. */ in r92c_iq_calib_chain()
135 uint16_t rx[2][2], struct r92c_iq_cal_reg_vals *vals) in r92c_iq_calib_run()
238 tx[chain], rx[chain]); in r92c_iq_calib_run()
[all …]
/freebsd/sys/dev/ath/
H A Dif_athioctl.h63 u_int32_t ast_rxorn; /* rx overrun interrupts */
64 u_int32_t ast_rxeol; /* rx eol interrupts */
93 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
94 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
95 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
96 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
97 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
98 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
99 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
100 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
[all …]

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