Lines Matching full:rx
73 #define CAS_CAW_RX_WGHT_MASK 0x00000003 /* RX DMA factor for... */
75 #define CAS_CAW_TX_WGHT_MASK 0x0000000c /* RX DMA factor for... */
91 #define CAS_INTR_RX_DONE 0x00000010 /* >=1 RX frames transferred. */
92 #define CAS_INTR_RX_BUF_NA 0x00000020 /* RX buffer not available */
93 #define CAS_INTR_RX_TAG_ERR 0x00000040 /* RX FIFO tag corrupted. */
94 #define CAS_INTR_RX_COMP_FULL 0x00000080 /* RX completion ring full */
95 #define CAS_INTR_RX_BUF_AEMPTY 0x00000100 /* RX desc. ring almost empty */
96 #define CAS_INTR_RX_COMP_AFULL 0x00000200 /* RX cmpl. ring almost full */
101 #define CAS_INTR_RX_MAC_INT 0x00008000 /* RX MAC interrupt */
130 #define CAS_RESET_RX 0x00000002 /* Reset RX DMA engine. */
166 #define CAS_INTRN_RX_DONE 0x00000001 /* >=1 RX frames transferred. */
167 #define CAS_INTRN_RX_COMP_FULL 0x00000002 /* RX completion ring full */
168 #define CAS_INTRN_RX_COMP_AFULL 0x00000004 /* RX cmpl. ring almost full */
169 #define CAS_INTRN_RX_BUF_NA 0x00000008 /* RX buffer not available */
170 #define CAS_INTRN_RX_BUF_AEMPTY 0x00000010 /* RX desc. ring almost empty */
281 /* RX DMA registers */
282 #define CAS_RX_CONF 0x4000 /* RX configuration */
283 #define CAS_RX_PSZ 0x4004 /* RX page size */
284 #define CAS_RX_FIFO_WR 0x4008 /* RX FIFO write pointer */
285 #define CAS_RX_FIFO_RD 0x400c /* RX FIFO read pointer */
286 #define CAS_RX_IPP_WR 0x4010 /* RX IPP FIFO write pointer */
287 #define CAS_RX_IPP_SDWR 0x4014 /* RX IPP FIFO shadow write pointer */
288 #define CAS_RX_IPP_RD 0x4018 /* RX IPP FIFO read pointer */
289 #define CAS_RX_DEBUG 0x401c /* RX debug */
290 #define CAS_RX_PTHRS 0x4020 /* RX PAUSE threshold */
291 #define CAS_RX_KICK 0x4024 /* RX kick */
292 #define CAS_RX_DESC_BASE_LO 0x4028 /* RX descriptor ring base low */
293 #define CAS_RX_DESC_BASE_HI 0x402c /* RX descriptor ring base high */
294 #define CAS_RX_COMP_BASE_LO 0x4030 /* RX completion ring base low */
295 #define CAS_RX_COMP_BASE_HI 0x4034 /* RX completion ring base high */
296 #define CAS_RX_COMP 0x4038 /* RX completion */
297 #define CAS_RX_COMP_HEAD 0x403c /* RX completion head */
298 #define CAS_RX_COMP_TAIL 0x4040 /* RX completion tail */
299 #define CAS_RX_BLANK 0x4044 /* RX blanking for ISR read */
300 #define CAS_RX_AEMPTY_THRS 0x4048 /* RX almost empty threshold */
301 #define CAS_RX_RED 0x4048 /* RX random early detection enable */
302 #define CAS_RX_FF 0x4050 /* RX FIFO fullness */
303 #define CAS_RX_IPP_PKT_CNT 0x4054 /* RX IPP packet counter */
304 #define CAS_RX_WORKING_DMA_LO 0x4058 /* RX working DMA pointer low */
305 #define CAS_RX_WORKING_DMA_HI 0x405c /* RX working DMA pointer high */
306 #define CAS_RX_BIST 0x4060 /* RX BIST */
307 #define CAS_RX_CTRL_FIFO_WR 0x4064 /* RX control FIFO write pointer */
308 #define CAS_RX_CTRL_FIFO_RD 0x4068 /* RX control FIFO read pointer */
309 #define CAS_RX_BLANK_ALIAS 0x406c /* RX blanking for ISR read alias */
310 #define CAS_RX_FIFO_ADDR 0x4080 /* RX FIFO address */
311 #define CAS_RX_FIFO_TAG 0x4084 /* RX FIFO tag */
312 #define CAS_RX_FIFO_DATA_LO 0x4088 /* RX FIFO data low */
313 #define CAS_RX_FIFO_DATA_HI_T0 0x408c /* RX FIFO data highT0 */
314 #define CAS_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data highT1 */
315 #define CAS_RX_CTRL_FIFO 0x4094 /* RX control FIFO and batching FIFO */
316 #define CAS_RX_CTRL_FIFO_LO 0x4098 /* RX control FIFO data low */
317 #define CAS_RX_CTRL_FIFO_MD 0x409c /* RX control FIFO data mid */
318 #define CAS_RX_CTRL_FIFO_HI 0x4100 /* RX control FIFO data high, flowID */
319 #define CAS_RX_IPP_ADDR 0x4104 /* RX IPP FIFO address */
320 #define CAS_RX_IPP_TAG 0x4108 /* RX IPP FIFO tag */
321 #define CAS_RX_IPP_DATA_LO 0x410c /* RX IPP FIFO data low */
322 #define CAS_RX_IPP_DATA_HI_T0 0x4110 /* RX IPP FIFO data highT0 */
323 #define CAS_RX_IPP_DATA_HI_T1 0x4114 /* RX IPP FIFO data highT1 */
324 #define CAS_RX_HDR_PAGE_LO 0x4118 /* RX header page pointer low */
325 #define CAS_RX_HDR_PAGE_HIGH 0x411c /* RX header page pointer high */
326 #define CAS_RX_MTU_PAGE_LO 0x4120 /* RX MTU page pointer low */
327 #define CAS_RX_MTU_PAGE_HIGH 0x4124 /* RX MTU page pointer high */
328 #define CAS_RX_REAS_DMA_ADDR 0x4128 /* RX reassembly DMA table address */
329 #define CAS_RX_REAS_DMA_DATA_LO 0x412c /* RX reassembly DMA table data low */
330 #define CAS_RX_REAS_DMA_DATA_MD 0x4130 /* RX reassembly DMA table data mid */
331 #define CAS_RX_REAS_DMA_DATA_HI 0x4134 /* RX reassembly DMA table data high */
332 /* The rest of the RX DMA registers are Cassini+/Saturn only. */
333 #define CAS_RX_DESC2_BASE_LO 0x4200 /* RX descriptor ring 2 base low */
334 #define CAS_RX_DESC2_BASE_HI 0x4204 /* RX descriptor ring 2 base high */
335 #define CAS_RX_COMP2_BASE_LO 0x4208 /* RX completion ring 2 base low */
336 #define CAS_RX_COMP2_BASE_HI 0x420c /* RX completion ring 2 base high */
337 #define CAS_RX_COMP3_BASE_LO 0x4210 /* RX completion ring 3 base low */
338 #define CAS_RX_COMP3_BASE_HI 0x4214 /* RX completion ring 3 base high */
339 #define CAS_RX_COMP4_BASE_LO 0x4218 /* RX completion ring 4 base low */
340 #define CAS_RX_COMP4_BASE_HI 0x421c /* RX completion ring 4 base high */
341 #define CAS_RX_KICK2 0x4220 /* RX kick 2 */
342 #define CAS_RX_COMP2 0x4224 /* RX completion 2 */
343 #define CAS_RX_COMP_HEAD2 0x4228 /* RX completion head 2 */
344 #define CAS_RX_COMP_TAIL2 0x422c /* RX completion tail 2 */
345 #define CAS_RX_COMP_HEAD3 0x4230 /* RX completion head 3 */
346 #define CAS_RX_COMP_TAIL3 0x4234 /* RX completion tail 3 */
347 #define CAS_RX_COMP_HEAD4 0x4238 /* RX completion head 4 */
348 #define CAS_RX_COMP_TAIL4 0x423c /* RX completion tail 4 */
349 #define CAS_RX_AEMPTY_THRS2 0x4048 /* RX almost empty threshold 2 */
351 #define CAS_RX_CONF_RXDMA_EN 0x00000001 /* RX DMA enable */
352 #define CAS_RX_CONF_DESC_MASK 0x0000001e /* RX descriptor ring size */
354 #define CAS_RX_CONF_COMP_MASK 0x000001e0 /* RX complition ring size */
359 /* The RX descriptor ring 2 is Cassini+/Saturn only. */
360 #define CAS_RX_CONF_DESC2_MASK 0x000f0000 /* RX descriptor ring 2 size */
373 #define CAS_RX_PSZ_MASK 0x00000003 /* RX page size */
397 #define CAS_RX_DESC_ALIGN 8192 /* RX descriptor alignment */
399 #define CAS_RX_COMP_ALIGN 8192 /* RX complition alignment */
401 /* The RX PAUSE thresholds are specified in multiples of 64 bytes. */
413 #define CAS_RX_BLANK_PKTS_MASK 0x000001ff /* RX blanking packets */
415 #define CAS_RX_BLANK_TIME_MASK 0x3ffff000 /* RX blanking time */
424 /* The RX random early detection probability is in 12.5% granularity. */
435 #define CAS_RX_FF_PKT_MASK 0x000000ff /* # of packets in RX FIFO */
439 #define CAS_RX_FF_FIFO_MASK 0x3ff80000 /* RX FIFO level */
561 #define CAS_MAC_RXRESET 0x6004 /* RX MAC software reset command */
564 #define CAS_MAC_RX_STATUS 0x6014 /* RX MAC status */
567 #define CAS_MAC_RX_MASK 0x6024 /* RX MAC mask */
570 #define CAS_MAC_RX_CONF 0x6034 /* RX MAC configuration */
659 #define CAS_MAC_RX_CODE_VIOL 0x61c8 /* RX code violation error counter */
680 #define CAS_MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */
681 #define CAS_MAC_RX_FRAME_EXP 0x00000004 /* RX frame counter wrap */
698 #define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */
706 #define CAS_MAC_RX_CONF_EN 0x00000001 /* RX enable */
718 #define CAS_MAC_CTRL_CONF_PASSP 0x00000004 /* Pass PAUSE up to RX DMA. */
847 #define CAS_PCS_SM_RX_CTRL_MASK 0x000000f0 /* RX control state */
886 #define CAS_PCS_PKT_CNT_RX_MASK 0x07ff0000 /* RX packets */
906 /* wired RX FIFO size in bytes */