104d19802SAdrian Chadd /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 3718cf2ccSPedro F. Giffuni * 404d19802SAdrian Chadd * Copyright (c) 2010-2011 Monthadar Al Jaberi, TerraNet AB 504d19802SAdrian Chadd * All rights reserved. 604d19802SAdrian Chadd * 704d19802SAdrian Chadd * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 804d19802SAdrian Chadd * All rights reserved. 904d19802SAdrian Chadd * 1004d19802SAdrian Chadd * Redistribution and use in source and binary forms, with or without 1104d19802SAdrian Chadd * modification, are permitted provided that the following conditions 1204d19802SAdrian Chadd * are met: 1304d19802SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 1404d19802SAdrian Chadd * notice, this list of conditions and the following disclaimer, 1504d19802SAdrian Chadd * without modification. 1604d19802SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1704d19802SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 1804d19802SAdrian Chadd * redistribution must be conditioned upon including a substantially 1904d19802SAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 2004d19802SAdrian Chadd * 2104d19802SAdrian Chadd * NO WARRANTY 2204d19802SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2304d19802SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2404d19802SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 2504d19802SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 2604d19802SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 2704d19802SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2804d19802SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2904d19802SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 3004d19802SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3104d19802SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3204d19802SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 3304d19802SAdrian Chadd */ 3404d19802SAdrian Chadd 3504d19802SAdrian Chadd /* 3604d19802SAdrian Chadd * Ioctl-related defintions for the Wireless TAP 3704d19802SAdrian Chadd * based on Atheros Wireless LAN controller driver. 3804d19802SAdrian Chadd */ 3904d19802SAdrian Chadd 4004d19802SAdrian Chadd #ifndef _DEV_WTAP_WTAPIOCTL_H 4104d19802SAdrian Chadd #define _DEV_WTAP_WTAPIOCTL_H 4204d19802SAdrian Chadd 43*fb1749ccSLi-Wen Hsu #include <sys/types.h> 4404d19802SAdrian Chadd #include <net80211/ieee80211_radiotap.h> 4504d19802SAdrian Chadd 4604d19802SAdrian Chadd #define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 4704d19802SAdrian Chadd #define SIOCZATHSTATS _IOWR('i', 139, struct ifreq) 4804d19802SAdrian Chadd 4904d19802SAdrian Chadd #define WTAPIOCTLCRT _IOW('W', 1, int) 5004d19802SAdrian Chadd #define WTAPIOCTLDEL _IOW('W', 2, int) 5104d19802SAdrian Chadd 5204d19802SAdrian Chadd struct wtap_stats { 5304d19802SAdrian Chadd u_int32_t ast_watchdog; /* device reset by watchdog */ 5404d19802SAdrian Chadd u_int32_t ast_hardware; /* fatal hardware error interrupts */ 5504d19802SAdrian Chadd u_int32_t ast_bmiss; /* beacon miss interrupts */ 5604d19802SAdrian Chadd u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */ 5704d19802SAdrian Chadd u_int32_t ast_bstuck; /* beacon stuck interrupts */ 5804d19802SAdrian Chadd u_int32_t ast_rxorn; /* rx overrun interrupts */ 5904d19802SAdrian Chadd u_int32_t ast_rxeol; /* rx eol interrupts */ 6004d19802SAdrian Chadd u_int32_t ast_txurn; /* tx underrun interrupts */ 6104d19802SAdrian Chadd u_int32_t ast_mib; /* mib interrupts */ 6204d19802SAdrian Chadd u_int32_t ast_intrcoal; /* interrupts coalesced */ 6304d19802SAdrian Chadd u_int32_t ast_tx_packets; /* packet sent on the interface */ 6404d19802SAdrian Chadd u_int32_t ast_tx_mgmt; /* management frames transmitted */ 6504d19802SAdrian Chadd u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 6604d19802SAdrian Chadd u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 6704d19802SAdrian Chadd u_int32_t ast_tx_encap; /* tx encapsulation failed */ 6804d19802SAdrian Chadd u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 6904d19802SAdrian Chadd u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 7004d19802SAdrian Chadd u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 7104d19802SAdrian Chadd u_int32_t ast_tx_linear; /* tx linearized to cluster */ 7204d19802SAdrian Chadd u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 7304d19802SAdrian Chadd u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 7404d19802SAdrian Chadd u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 7504d19802SAdrian Chadd u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 7604d19802SAdrian Chadd u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 7704d19802SAdrian Chadd u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 7804d19802SAdrian Chadd u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 7904d19802SAdrian Chadd u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 8004d19802SAdrian Chadd u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 8104d19802SAdrian Chadd u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 8204d19802SAdrian Chadd u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 8304d19802SAdrian Chadd u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 8404d19802SAdrian Chadd u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 8504d19802SAdrian Chadd u_int32_t ast_tx_protect; /* tx frames with protection */ 8604d19802SAdrian Chadd u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ 8704d19802SAdrian Chadd u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ 8804d19802SAdrian Chadd u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 8904d19802SAdrian Chadd u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 9004d19802SAdrian Chadd u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 9104d19802SAdrian Chadd u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 9204d19802SAdrian Chadd u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 9304d19802SAdrian Chadd u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 9404d19802SAdrian Chadd u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 9504d19802SAdrian Chadd u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 9604d19802SAdrian Chadd u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ 9704d19802SAdrian Chadd u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 9804d19802SAdrian Chadd u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 9904d19802SAdrian Chadd u_int32_t ast_rx_packets; /* packet recv on the interface */ 10004d19802SAdrian Chadd u_int32_t ast_rx_mgt; /* management frames received */ 10104d19802SAdrian Chadd u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 10204d19802SAdrian Chadd int8_t ast_tx_rssi; /* tx rssi of last ack */ 10304d19802SAdrian Chadd int8_t ast_rx_rssi; /* rx rssi from histogram */ 10404d19802SAdrian Chadd u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */ 10504d19802SAdrian Chadd u_int32_t ast_be_xmit; /* beacons transmitted */ 10604d19802SAdrian Chadd u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 10704d19802SAdrian Chadd u_int32_t ast_per_cal; /* periodic calibration calls */ 10804d19802SAdrian Chadd u_int32_t ast_per_calfail;/* periodic calibration failed */ 10904d19802SAdrian Chadd u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 11004d19802SAdrian Chadd u_int32_t ast_rate_calls; /* rate control checks */ 11104d19802SAdrian Chadd u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 11204d19802SAdrian Chadd u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 11304d19802SAdrian Chadd u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 11404d19802SAdrian Chadd u_int32_t ast_ant_txswitch;/* tx antenna switches */ 11504d19802SAdrian Chadd u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ 11604d19802SAdrian Chadd u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ 11704d19802SAdrian Chadd u_int32_t ast_cabq_xmit; /* cabq frames transmitted */ 11804d19802SAdrian Chadd u_int32_t ast_cabq_busy; /* cabq found busy */ 11904d19802SAdrian Chadd u_int32_t ast_tx_raw; /* tx frames through raw api */ 12004d19802SAdrian Chadd u_int32_t ast_ff_txok; /* fast frames tx'd successfully */ 12104d19802SAdrian Chadd u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */ 12204d19802SAdrian Chadd u_int32_t ast_ff_rx; /* fast frames rx'd */ 12304d19802SAdrian Chadd u_int32_t ast_ff_flush; /* fast frames flushed from staging q */ 12404d19802SAdrian Chadd u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */ 12504d19802SAdrian Chadd int8_t ast_rx_noise; /* rx noise floor */ 12604d19802SAdrian Chadd u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */ 12704d19802SAdrian Chadd u_int32_t ast_tdma_update;/* TDMA slot timing updates */ 12804d19802SAdrian Chadd u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */ 12904d19802SAdrian Chadd u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */ 13004d19802SAdrian Chadd u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/ 13104d19802SAdrian Chadd u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/ 13204d19802SAdrian Chadd u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 13304d19802SAdrian Chadd u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 13404d19802SAdrian Chadd u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 13504d19802SAdrian Chadd u_int32_t ast_be_missed; /* missed beacons */ 13604d19802SAdrian Chadd u_int32_t ast_pad[13]; 13704d19802SAdrian Chadd }; 13804d19802SAdrian Chadd 13904d19802SAdrian Chadd /* 14004d19802SAdrian Chadd * Radio capture format. 14104d19802SAdrian Chadd */ 14204d19802SAdrian Chadd #define WTAP_RX_RADIOTAP_PRESENT ( \ 14304d19802SAdrian Chadd 0) 14404d19802SAdrian Chadd 14504d19802SAdrian Chadd struct wtap_rx_radiotap_header { 14604d19802SAdrian Chadd struct ieee80211_radiotap_header wr_ihdr; 14704d19802SAdrian Chadd #if 0 14804d19802SAdrian Chadd u_int64_t wr_tsf; 14904d19802SAdrian Chadd u_int8_t wr_flags; 15004d19802SAdrian Chadd u_int8_t wr_rate; 15104d19802SAdrian Chadd int8_t wr_antsignal; 15204d19802SAdrian Chadd int8_t wr_antnoise; 15304d19802SAdrian Chadd u_int8_t wr_antenna; 15404d19802SAdrian Chadd u_int8_t wr_pad[3]; 15504d19802SAdrian Chadd u_int32_t wr_chan_flags; 15604d19802SAdrian Chadd u_int16_t wr_chan_freq; 15704d19802SAdrian Chadd u_int8_t wr_chan_ieee; 15804d19802SAdrian Chadd int8_t wr_chan_maxpow; 15904d19802SAdrian Chadd #endif 160786ac703SAndriy Voskoboinyk } __packed __aligned(8); 16104d19802SAdrian Chadd 16204d19802SAdrian Chadd #define WTAP_TX_RADIOTAP_PRESENT ( \ 16304d19802SAdrian Chadd 0) 16404d19802SAdrian Chadd 16504d19802SAdrian Chadd struct wtap_tx_radiotap_header { 16604d19802SAdrian Chadd struct ieee80211_radiotap_header wt_ihdr; 16704d19802SAdrian Chadd #if 0 16804d19802SAdrian Chadd u_int8_t wt_flags; 16904d19802SAdrian Chadd u_int8_t wt_rate; 17004d19802SAdrian Chadd u_int8_t wt_txpower; 17104d19802SAdrian Chadd u_int8_t wt_antenna; 17204d19802SAdrian Chadd u_int32_t wt_chan_flags; 17304d19802SAdrian Chadd u_int16_t wt_chan_freq; 17404d19802SAdrian Chadd u_int8_t wt_chan_ieee; 17504d19802SAdrian Chadd int8_t wt_chan_maxpow; 17604d19802SAdrian Chadd #endif 17704d19802SAdrian Chadd } __packed; 17804d19802SAdrian Chadd 17904d19802SAdrian Chadd #endif 180