Lines Matching full:rx
88 #define E1000_RCTL 0x00100 /* Rx Control - RW */
91 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
148 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
152 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
153 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
154 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
155 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
156 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
157 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
159 /* Split and Replication Rx Control - RW */
160 #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
161 #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
162 #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
163 #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
164 #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
166 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
168 #define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */
169 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
170 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
284 #define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
340 #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
342 #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
344 #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
345 #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
346 #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
347 #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
348 #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
349 #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
350 #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
351 #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
352 #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
353 #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
355 #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
356 #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
359 #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
360 #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
361 #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
362 #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
363 #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
364 #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
367 #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
368 #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
371 #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
385 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
386 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
391 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */
421 #define E1000_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */
422 #define E1000_LSECRXOCTD 0x0431C /* Rx Octets Decrypted Count */
423 #define E1000_LSECRXOCTV 0x04320 /* Rx Octets Validated */
424 #define E1000_LSECRXBAD 0x04324 /* Rx Bad Tag */
425 #define E1000_LSECRXNOSCI 0x04328 /* Rx Packet No SCI Count */
426 #define E1000_LSECRXUNSCI 0x0432C /* Rx Packet Unknown SCI Count */
427 #define E1000_LSECRXUNCH 0x04330 /* Rx Unchecked Packets Count */
428 #define E1000_LSECRXDELAY 0x04340 /* Rx Delayed Packet Count */
429 #define E1000_LSECRXLATE 0x04350 /* Rx Late Packets Count */
430 #define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */
431 #define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */
432 #define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */
433 #define E1000_LSECRXUNSA 0x043C0 /* Rx Unused SA Count */
434 #define E1000_LSECRXNUSA 0x043D0 /* Rx Not Using SA Count */
436 #define E1000_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */
438 #define E1000_LSECRXCTRL 0x0B304 /* Rx Control - RW */
444 #define E1000_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */
445 #define E1000_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */
450 #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
451 #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
452 /* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
459 #define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */
460 #define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */
461 /* IPSec Rx IPv4/v6 Address - RW */
463 /* IPSec Rx 128-bit Key - RW */
465 #define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */
466 #define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */
476 #define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */
477 #define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */
478 #define E1000_RPTHC 0x04104 /* Rx Packets To Host */
492 #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
493 #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */
497 #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */
559 #define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
600 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
602 #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
603 #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
604 #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
605 #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */
606 #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */
622 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
623 #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
644 #define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */
645 #define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */
651 /* Rx Packet plane TC Rate-Scheduler Config */
661 /* Rx Packet plane TC Rate-Scheduler Status */
663 /* Rx Packet plane TC Rate-Scheduler MMW */
677 #define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */
689 #define E1000_DMCCNT 0x05DD4 /* Current Rx Count */
690 #define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */
711 #define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */