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/linux/arch/sparc/kernel/
H A Dpci_sun4v.c80 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
119 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
127 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n", in iommu_batch_flush()
218 tbl = &iommu->atu->tbl; in dma_4v_alloc_coherent()
328 struct atu *atu; in dma_4v_free_coherent() local
337 atu = iommu->atu; in dma_4v_free_coherent()
344 tbl = &atu->tbl; in dma_4v_free_coherent()
345 iotsb_num = atu->iotsb->iotsb_num; in dma_4v_free_coherent()
360 struct atu *atu; in dma_4v_map_phys() local
379 atu = iommu->atu; in dma_4v_map_phys()
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-designware-host.c424 struct dw_pcie_ob_atu_cfg atu = {0}; in dw_pcie_config_ecam_iatu() local
437 atu.index = 0; in dw_pcie_config_ecam_iatu()
438 atu.type = PCIE_ATU_TYPE_CFG0; in dw_pcie_config_ecam_iatu()
439 atu.parent_bus_addr = pp->cfg0_base + SZ_1M; in dw_pcie_config_ecam_iatu()
441 atu.size = SZ_1M; in dw_pcie_config_ecam_iatu()
442 atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; in dw_pcie_config_ecam_iatu()
443 ret = dw_pcie_prog_outbound_atu(pci, &atu); in dw_pcie_config_ecam_iatu()
453 atu.index = 1; in dw_pcie_config_ecam_iatu()
454 atu.type = PCIE_ATU_TYPE_CFG1; in dw_pcie_config_ecam_iatu()
455 atu.parent_bus_addr = pp->cfg0_base + SZ_2M; in dw_pcie_config_ecam_iatu()
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal1_atu.c3 * Marvell 88E6xxx Address Translation Unit (ATU) support
18 /* Offset 0x01: ATU FID Register */
25 /* Offset 0x0A: ATU Control Register */
110 /* Offset 0x0B: ATU Operation Register */
144 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_op()
156 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_op()
160 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_op()
192 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ in mv88e6xxx_g1_atu_fid_read()
200 /* ATU DBNum[5:4] are located in ATU Operation 9:8 */ in mv88e6xxx_g1_atu_fid_read()
204 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ in mv88e6xxx_g1_atu_fid_read()
[all …]
H A Dglobal1.h44 /* Offset 0x01: ATU FID Register */
112 /* Offset 0x0A: ATU Control Register */
117 /* Offset 0x0B: ATU Operation Register */
134 /* Offset 0x0C: ATU Data Register */
166 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
167 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
168 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
H A Ddevlink.c112 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); in mv88e6xxx_devlink_atu_bin_get()
118 dev_err(chip->dev, "failed to perform ATU get next\n"); in mv88e6xxx_devlink_atu_bin_get()
124 dev_err(chip->dev, "failed to get ATU stats\n"); in mv88e6xxx_devlink_atu_bin_get()
187 err = dsa_devlink_resource_register(ds, "ATU", in mv88e6xxx_setup_devlink_resources()
304 /* The ATU entry varies between mv88e6xxx chipset generations. Define
664 .name = "atu",
/linux/arch/sparc/include/asm/
H A Diommu_64.h30 /* Data structures for SPARC ATU architecture */
46 struct atu { struct
57 struct atu *atu; argument
/linux/Documentation/devicetree/bindings/pci/
H A Dintel,keembay-pcie-ep.yaml24 - const: atu
62 reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
H A Dti,am65-pci-ep.yaml29 - const: atu
70 reg-names = "app", "dbics", "addr_space", "atu";
H A Dhost-generic-pci.yaml68 DesignWare PCIe controller in RC mode with static ATU window mappings
72 is there any reason for the driver to reconfigure ATU windows for
75 In cases where the IP was synthesized with a minimum ATU window size
H A Dst,stm32-pcie-ep.yaml34 - const: atu
63 reg-names = "dbi", "dbi2", "atu", "addr_space";
H A Dintel,keembay-pcie.yaml32 - const: atu
83 reg-names = "dbi", "atu", "config", "apb";
H A Drcar-gen4-pci-ep.yaml32 - const: atu
104 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
H A Dsophgo,sg2044-pcie.yaml35 - const: atu
98 reg-names = "dbi", "atu", "config", "app";
H A Drockchip-dw-pcie-ep.yaml41 - const: atu
68 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
H A Drcar-gen4-pci-host.yaml32 - const: atu
102 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
H A Damd,versal2-mdb-host.yaml32 - const: atu
112 reg-names = "slcr", "config", "dbi", "atu";
H A Dti,am65-pci-host.yaml32 - const: atu
130 reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp";
H A Dsnps,dw-pcie-ep.yaml76 const: atu
104 - description: See native 'atu' CSR region for details.
H A Dsnps,dw-pcie.yaml85 const: atu
112 - description: See native 'atu' CSR region for details.
H A Dsocionext,uniphier-pcie-ep.yaml35 - const: atu
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi41 reg-names = "dbi", "atu", "config", "app";
76 reg-names = "dbi", "atu", "config", "app";
111 reg-names = "dbi", "atu", "config", "app";
146 reg-names = "dbi", "atu", "config", "app";
181 reg-names = "dbi", "atu", "config", "app";
/linux/drivers/pci/controller/
H A Dpcie-rockchip-host.c800 dev_err(dev, "program RC mem outbound ATU failed\n"); in rockchip_pcie_cfg_atu()
807 dev_err(dev, "program RC mem inbound ATU failed\n"); in rockchip_pcie_cfg_atu()
815 /* store the register number offset to program RC io outbound ATU */ in rockchip_pcie_cfg_atu()
829 dev_err(dev, "program RC io outbound ATU failed\n"); in rockchip_pcie_cfg_atu()
/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst66 (ATU) and to indicate the link status. Endpoint can indicate the status of
117 the outbound ATU such that transactions to Doorbell BAR will be routed
128 will configure the outbound ATU such that transactions to MW BAR
/linux/drivers/pci/controller/plda/
H A Dpcie-starfive.c70 * internal registers, such as interrupt, DMA and ATU registers...
353 * The 64-bits prefetchable address translation configurations in ATU in starfive_pcie_host_init()
/linux/sound/soc/sof/amd/
H A Dacp-stream.c121 /* Flush ATU Cache after PTE Update */ in acp_dsp_stream_config()

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