xref: /linux/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml (revision 0bd0a41a5120f78685a132834865b0a631b9026a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: DesignWare based PCIe Root Complex controller on Sophgo SoCs
8
9maintainers:
10  - Inochi Amaoto <inochiama@gmail.com>
11
12description:
13  SG2044 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
14  PCIe IP and thus inherits all the common properties defined in
15  snps,dw-pcie.yaml.
16
17allOf:
18  - $ref: /schemas/pci/pci-host-bridge.yaml#
19  - $ref: /schemas/pci/snps,dw-pcie.yaml#
20
21properties:
22  compatible:
23    const: sophgo,sg2044-pcie
24
25  reg:
26    items:
27      - description: Data Bus Interface (DBI) registers
28      - description: iATU registers
29      - description: Config registers
30      - description: Sophgo designed configuration registers
31
32  reg-names:
33    items:
34      - const: dbi
35      - const: atu
36      - const: config
37      - const: app
38
39  clocks:
40    items:
41      - description: core clk
42
43  clock-names:
44    items:
45      - const: core
46
47  interrupt-controller:
48    description: Interrupt controller node for handling legacy PCI interrupts.
49    type: object
50
51    properties:
52      "#address-cells":
53        const: 0
54
55      "#interrupt-cells":
56        const: 1
57
58      interrupt-controller: true
59
60      interrupts:
61        items:
62          - description: combined legacy interrupt
63
64    required:
65      - "#address-cells"
66      - "#interrupt-cells"
67      - interrupt-controller
68      - interrupts
69
70    additionalProperties: false
71
72  msi-parent: true
73
74  ranges:
75    maxItems: 5
76
77required:
78  - compatible
79  - reg
80  - clocks
81
82unevaluatedProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/interrupt-controller/irq.h>
87
88    soc {
89      #address-cells = <2>;
90      #size-cells = <2>;
91
92      pcie@6c00400000 {
93        compatible = "sophgo,sg2044-pcie";
94        reg = <0x6c 0x00400000 0x0 0x00001000>,
95              <0x6c 0x00700000 0x0 0x00004000>,
96              <0x40 0x00000000 0x0 0x00001000>,
97              <0x6c 0x00780c00 0x0 0x00000400>;
98        reg-names = "dbi", "atu", "config", "app";
99        #address-cells = <3>;
100        #size-cells = <2>;
101        bus-range = <0x00 0xff>;
102        clocks = <&clk 0>;
103        clock-names = "core";
104        device_type = "pci";
105        linux,pci-domain = <0>;
106        msi-parent = <&msi>;
107        ranges = <0x01000000 0x0  0x00000000  0x40 0x10000000  0x0 0x00200000>,
108                 <0x42000000 0x0  0x00000000  0x0  0x00000000  0x0 0x04000000>,
109                 <0x02000000 0x0  0x04000000  0x0  0x04000000  0x0 0x04000000>,
110                 <0x43000000 0x42 0x00000000  0x42 0x00000000  0x2 0x00000000>,
111                 <0x03000000 0x41 0x00000000  0x41 0x00000000  0x1 0x00000000>;
112
113        interrupt-controller {
114          #address-cells = <0>;
115          #interrupt-cells = <1>;
116          interrupt-controller;
117          interrupt-parent = <&intc>;
118          interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
119        };
120      };
121    };
122...
123