1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare PCIe interface 8 9maintainers: 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 12 13description: | 14 Synopsys DesignWare PCIe host controller 15 16# Please create a separate DT-schema for your DWC PCIe Root Port controller 17# and make sure it's assigned with the vendor-specific compatible string. 18select: 19 properties: 20 compatible: 21 const: snps,dw-pcie 22 required: 23 - compatible 24 25allOf: 26 - $ref: /schemas/pci/pci-host-bridge.yaml# 27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml# 28 - if: 29 not: 30 required: 31 - msi-map 32 then: 33 properties: 34 interrupt-names: 35 contains: 36 const: msi 37 38properties: 39 reg: 40 description: 41 At least DBI reg-space and peripheral devices CFG-space outbound window 42 are required for the normal controller work. iATU memory IO region is 43 also required if the space is unrolled (IP-core version >= 4.80a). 44 minItems: 2 45 maxItems: 7 46 47 reg-names: 48 minItems: 2 49 maxItems: 7 50 items: 51 oneOf: 52 - description: 53 Basic DWC PCIe controller configuration-space accessible over 54 the DBI interface. This memory space is either activated with 55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region 56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible 57 via the PL viewports on the DWC PCIe controllers older than 58 v4.80a. 59 const: dbi 60 - description: 61 Shadow DWC PCIe config-space registers. This space is selected 62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of 63 the PCI-SIG PCIe CFG-space with the shadow registers for some 64 PCI Header space, PCI Standard and Extended Structures. It's 65 mainly relevant for the end-point controller configuration, 66 but still there are some shadow registers available for the 67 Root Port mode too. 68 const: dbi2 69 - description: 70 External Local Bus registers. It's an application-dependent 71 registers normally defined by the platform engineers. The space 72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can 73 be accessed over some platform-specific means (for instance 74 as a part of a system controller). 75 enum: [ elbi, app ] 76 - description: 77 iATU/eDMA registers common for all device functions. It's an 78 unrolled memory space with the internal Address Translation 79 Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1 80 and CS2 = 1. For IP-core releases prior v4.80a, these registers 81 have been programmed via an indirect addressing scheme using a 82 set of viewport CSRs mapped into the PL space. Note iATU is 83 normally mapped to the 0x0 address of this region, while eDMA 84 is available at 0x80000 base address. 85 const: atu 86 - description: 87 Platform-specific eDMA registers. Some platforms may have eDMA 88 CSRs mapped in a non-standard base address. The registers offset 89 can be changed or the MS/LS-bits of the address can be attached 90 in an additional RTL block before the MEM-IO transactions reach 91 the DW PCIe slave interface. 92 const: dma 93 - description: 94 PHY/PCS configuration registers. Some platforms can have the 95 PCS and PHY CSRs accessible over a dedicated memory mapped 96 region, but mainly these registers are indirectly accessible 97 either by means of the embedded PHY viewport schema or by some 98 platform-specific method. 99 const: phy 100 - description: 101 Outbound iATU-capable memory-region which will be used to access 102 the peripheral PCIe devices configuration space. 103 const: config 104 - description: 105 Vendor-specific CSR names. Consider using the generic names above 106 for new bindings. 107 oneOf: 108 - description: See native 'elbi/app' CSR region for details. 109 enum: [ apb, mgmt, link, ulreg, appl ] 110 - description: See native 'atu' CSR region for details. 111 enum: [ atu_dma ] 112 - description: Syscon-related CSR regions. 113 enum: [ smu, mpu ] 114 - description: Tegra234 aperture 115 enum: [ ecam ] 116 - description: AMD MDB PCIe SLCR region 117 const: slcr 118 allOf: 119 - contains: 120 const: dbi 121 - contains: 122 const: config 123 124 interrupts: 125 description: 126 DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt 127 signal is supposed to be specified for the host controller. 128 minItems: 1 129 maxItems: 26 130 131 interrupt-names: 132 minItems: 1 133 maxItems: 26 134 items: 135 oneOf: 136 - description: 137 Controller request to read or write virtual product data 138 from/to the VPD capability registers. 139 const: vpd 140 - description: 141 Link Equalization Request flag is set in the Link Status 2 142 register (applicable if the corresponding IRQ is enabled in 143 the Link Control 3 register). 144 const: l_eq 145 - description: 146 Indicates that the eDMA Tx/Rx transfer is complete or that an 147 error has occurred on the corresponding channel. eDMA can have 148 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up 149 to 16 IRQ signals all together. Write eDMA channels shall go 150 first in the ordered row as per default edma_int[*] bus setup. 151 pattern: '^dma([0-9]|1[0-5])?$' 152 - description: 153 PCIe protocol correctable error or a Data Path protection 154 correctable error is detected by the automotive/safety 155 feature. 156 const: sft_ce 157 - description: 158 Indicates that the internal safety mechanism has detected an 159 uncorrectable error. 160 const: sft_ue 161 - description: 162 Application-specific IRQ raised depending on the vendor-specific 163 events basis. 164 const: app 165 - description: 166 DSP AXI MSI Interrupt detected. It gets de-asserted when there is 167 no more MSI interrupt pending. The interrupt is relevant to the 168 iMSI-RX - Integrated MSI Receiver (AXI bridge). 169 const: msi 170 - description: 171 Legacy A/B/C/D interrupt signal. Basically it's triggered by 172 receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message 173 from the downstream device. 174 pattern: "^int(a|b|c|d)$" 175 - description: 176 Error condition detected and a flag is set in the Root Error Status 177 register of the AER capability. It's asserted when the RC 178 internally generated an error or an error message is received by 179 the RC. 180 const: aer 181 - description: 182 PME message is received by the port. That means having the PME 183 status bit set in the Root Status register (the event is 184 supposed to be unmasked in the Root Control register). 185 const: pme 186 - description: 187 Hot-plug event is detected. That is a bit has been set in the 188 Slot Status register and the corresponding event is enabled in 189 the Slot Control register. 190 const: hp 191 - description: 192 Link Autonomous Bandwidth Status flag has been set in the Link 193 Status register (the event is supposed to be unmasked in the 194 Link Control register). 195 const: bw_au 196 - description: 197 Bandwidth Management Status flag has been set in the Link 198 Status register (the event is supposed to be unmasked in the 199 Link Control register). 200 const: bw_mg 201 - description: 202 Combined Legacy A/B/C/D interrupt signal. See "^int(a|b|c|d)$" for 203 details. 204 const: legacy 205 - description: 206 Vendor-specific IRQ names. Consider using the generic names above 207 for new bindings. 208 oneOf: 209 - description: See native "app" IRQ for details 210 enum: [ intr, sys, pmc, msg, err ] 211 212additionalProperties: true 213 214required: 215 - compatible 216 - reg 217 - reg-names 218 219examples: 220 - | 221 pcie@dfc00000 { 222 compatible = "snps,dw-pcie"; 223 device_type = "pci"; 224 reg = <0xdfc00000 0x0001000>, /* IP registers */ 225 <0xd0000000 0x0002000>; /* Configuration space */ 226 reg-names = "dbi", "config"; 227 #address-cells = <3>; 228 #size-cells = <2>; 229 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, 230 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; 231 bus-range = <0x0 0xff>; 232 233 interrupts = <25>, <24>; 234 interrupt-names = "msi", "hp"; 235 236 reset-gpios = <&port0 0 1>; 237 238 phys = <&pcie_phy>; 239 phy-names = "pcie"; 240 241 num-lanes = <1>; 242 max-link-speed = <3>; 243 }; 244