1bad659dfSYoshihiro Shimoda# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2bad659dfSYoshihiro Shimoda# Copyright (C) 2022-2023 Renesas Electronics Corp. 3bad659dfSYoshihiro Shimoda%YAML 1.2 4bad659dfSYoshihiro Shimoda--- 5bad659dfSYoshihiro Shimoda$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml# 6bad659dfSYoshihiro Shimoda$schema: http://devicetree.org/meta-schemas/core.yaml# 7bad659dfSYoshihiro Shimoda 8bad659dfSYoshihiro Shimodatitle: Renesas R-Car Gen4 PCIe Endpoint 9bad659dfSYoshihiro Shimoda 10bad659dfSYoshihiro Shimodamaintainers: 11bad659dfSYoshihiro Shimoda - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 12bad659dfSYoshihiro Shimoda 13bad659dfSYoshihiro ShimodaallOf: 14bad659dfSYoshihiro Shimoda - $ref: snps,dw-pcie-ep.yaml# 15bad659dfSYoshihiro Shimoda 16bad659dfSYoshihiro Shimodaproperties: 17bad659dfSYoshihiro Shimoda compatible: 18bad659dfSYoshihiro Shimoda items: 19c037263dSYoshihiro Shimoda - enum: 20c037263dSYoshihiro Shimoda - renesas,r8a779f0-pcie-ep # R-Car S4-8 21c037263dSYoshihiro Shimoda - renesas,r8a779g0-pcie-ep # R-Car V4H 22*05a01639SYoshihiro Shimoda - renesas,r8a779h0-pcie-ep # R-Car V4M 23bad659dfSYoshihiro Shimoda - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4 24bad659dfSYoshihiro Shimoda 25bad659dfSYoshihiro Shimoda reg: 26bad659dfSYoshihiro Shimoda maxItems: 7 27bad659dfSYoshihiro Shimoda 28bad659dfSYoshihiro Shimoda reg-names: 29bad659dfSYoshihiro Shimoda items: 30bad659dfSYoshihiro Shimoda - const: dbi 31bad659dfSYoshihiro Shimoda - const: dbi2 32bad659dfSYoshihiro Shimoda - const: atu 33bad659dfSYoshihiro Shimoda - const: dma 34bad659dfSYoshihiro Shimoda - const: app 35bad659dfSYoshihiro Shimoda - const: phy 36bad659dfSYoshihiro Shimoda - const: addr_space 37bad659dfSYoshihiro Shimoda 38bad659dfSYoshihiro Shimoda interrupts: 39bad659dfSYoshihiro Shimoda maxItems: 3 40bad659dfSYoshihiro Shimoda 41bad659dfSYoshihiro Shimoda interrupt-names: 42bad659dfSYoshihiro Shimoda items: 43bad659dfSYoshihiro Shimoda - const: dma 44bad659dfSYoshihiro Shimoda - const: sft_ce 45bad659dfSYoshihiro Shimoda - const: app 46bad659dfSYoshihiro Shimoda 47bad659dfSYoshihiro Shimoda clocks: 48bad659dfSYoshihiro Shimoda maxItems: 2 49bad659dfSYoshihiro Shimoda 50bad659dfSYoshihiro Shimoda clock-names: 51bad659dfSYoshihiro Shimoda items: 52bad659dfSYoshihiro Shimoda - const: core 53bad659dfSYoshihiro Shimoda - const: ref 54bad659dfSYoshihiro Shimoda 55bad659dfSYoshihiro Shimoda power-domains: 56bad659dfSYoshihiro Shimoda maxItems: 1 57bad659dfSYoshihiro Shimoda 58bad659dfSYoshihiro Shimoda resets: 59bad659dfSYoshihiro Shimoda maxItems: 1 60bad659dfSYoshihiro Shimoda 61bad659dfSYoshihiro Shimoda reset-names: 62bad659dfSYoshihiro Shimoda items: 63bad659dfSYoshihiro Shimoda - const: pwr 64bad659dfSYoshihiro Shimoda 65bad659dfSYoshihiro Shimoda max-link-speed: 66bad659dfSYoshihiro Shimoda maximum: 4 67bad659dfSYoshihiro Shimoda 68bad659dfSYoshihiro Shimoda num-lanes: 69bad659dfSYoshihiro Shimoda maximum: 4 70bad659dfSYoshihiro Shimoda 71bad659dfSYoshihiro Shimoda max-functions: 72bad659dfSYoshihiro Shimoda maximum: 2 73bad659dfSYoshihiro Shimoda 74bad659dfSYoshihiro Shimodarequired: 75bad659dfSYoshihiro Shimoda - compatible 76bad659dfSYoshihiro Shimoda - reg 77bad659dfSYoshihiro Shimoda - reg-names 78bad659dfSYoshihiro Shimoda - interrupts 79bad659dfSYoshihiro Shimoda - interrupt-names 80bad659dfSYoshihiro Shimoda - clocks 81bad659dfSYoshihiro Shimoda - clock-names 82bad659dfSYoshihiro Shimoda - power-domains 83bad659dfSYoshihiro Shimoda - resets 84bad659dfSYoshihiro Shimoda - reset-names 85bad659dfSYoshihiro Shimoda 86bad659dfSYoshihiro ShimodaunevaluatedProperties: false 87bad659dfSYoshihiro Shimoda 88bad659dfSYoshihiro Shimodaexamples: 89bad659dfSYoshihiro Shimoda - | 90bad659dfSYoshihiro Shimoda #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 91bad659dfSYoshihiro Shimoda #include <dt-bindings/interrupt-controller/arm-gic.h> 92bad659dfSYoshihiro Shimoda #include <dt-bindings/power/r8a779f0-sysc.h> 93bad659dfSYoshihiro Shimoda 94bad659dfSYoshihiro Shimoda soc { 95bad659dfSYoshihiro Shimoda #address-cells = <2>; 96bad659dfSYoshihiro Shimoda #size-cells = <2>; 97bad659dfSYoshihiro Shimoda 98bad659dfSYoshihiro Shimoda pcie0_ep: pcie-ep@e65d0000 { 99bad659dfSYoshihiro Shimoda compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep"; 100bad659dfSYoshihiro Shimoda reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, 101bad659dfSYoshihiro Shimoda <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 102bad659dfSYoshihiro Shimoda <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 103bad659dfSYoshihiro Shimoda <0 0xfe000000 0 0x400000>; 104bad659dfSYoshihiro Shimoda reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; 105bad659dfSYoshihiro Shimoda interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 106bad659dfSYoshihiro Shimoda <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 107bad659dfSYoshihiro Shimoda <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 108bad659dfSYoshihiro Shimoda interrupt-names = "dma", "sft_ce", "app"; 109bad659dfSYoshihiro Shimoda clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 110bad659dfSYoshihiro Shimoda clock-names = "core", "ref"; 111bad659dfSYoshihiro Shimoda power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 112bad659dfSYoshihiro Shimoda resets = <&cpg 624>; 113bad659dfSYoshihiro Shimoda reset-names = "pwr"; 114bad659dfSYoshihiro Shimoda max-link-speed = <4>; 115bad659dfSYoshihiro Shimoda num-lanes = <2>; 116bad659dfSYoshihiro Shimoda max-functions = /bits/ 8 <2>; 117bad659dfSYoshihiro Shimoda }; 118bad659dfSYoshihiro Shimoda }; 119