Home
last modified time | relevance | path

Searched +full:5 +full:gbase +full:- +full:x (Results 1 – 25 of 27) sorted by relevance

12

/linux/include/uapi/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
23 #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
37 #define MDIO_DEVS1 5 /* Devices in package */
50 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
[all …]
/linux/Documentation/networking/
H A Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
208 Now just make sure that phydev->supported and phydev->advertising have any
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
93 err = t3_mdio_change_bits(phy, rv->mmd_addr, in set_phy_regs()
94 rv->reg_addr, rv->clear_bits, in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Dcn9132-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9132-sr-cex7.dtsi"
19 compatible = "solidrun,cn9132-clearfog",
20 "solidrun,cn9132-sr-cex7", "marvell,cn9130";
32 gpio-keys {
33 compatible = "gpio-keys";
[all …]
/linux/drivers/phy/microchip/
H A Dlan966x_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
21 gbase, ginst, gcnt, gwidth, \ argument
23 (gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth))
80 SERDES_MUX_QSGMII(SERDES6G(2), 5, HSIO_HW_CFG_QSGMII_ENA,
113 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
118 HSIO_HW_CFG_GMII_ENA_SET(BIT(5))),
189 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) | in lan966x_sd6g40_reg_cfg()
190 HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) | in lan966x_sd6g40_reg_cfg()
191 HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) | in lan966x_sd6g40_reg_cfg()
[all …]
/linux/drivers/net/phy/
H A Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
178 return phydev->drv->driver_data; in to_mv3310_chip()
[all …]
H A Dbcm84881.c1 // SPDX-License-Identifier: GPL-2.0
2 // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
5 // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
6 // interface according to the operating speed between 10GBASE-R,
7 // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
34 unsigned long *possible = phydev->possible_interfaces; in bcm84881_fill_possible_interfaces()
45 switch (phydev->interface) { in bcm84881_config_init()
51 return -ENODEV; in bcm84881_config_init()
62 if (!phydev->is_c45 || in bcm84881_probe()
63 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in bcm84881_probe()
[all …]
H A Dair_en8811h.c1 // SPDX-License-Identifier: GPL-2.0+
6 * - Only full duplex supported
7 * - Forced speed (AN off) is not supported by hardware (100Mbps)
85 #define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */
97 #define AIR_PHY_LED_BLINK_10RX BIT(5)
116 #define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
128 * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx
129 * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps
130 * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps
246 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_buckpbus_reg_write()
[all …]
H A Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
44 * struct phylink - internal data type for phylink
60 u8 link_port; /* The current non-phy ethtool port */
92 if ((pl)->config->type == PHYLINK_NETDEV) \
93 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
94 else if ((pl)->config->type == PHYLINK_DEV) \
95 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
107 if ((pl)->config->type == PHYLINK_NETDEV) \
108 netdev_dbg((pl)->netdev, fmt, ##__VA_ARGS__); \
[all …]
/linux/include/linux/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
82 * Set phydev->irq to PHY_POLL if interrupts are not supported,
86 #define PHY_POLL -1
87 #define PHY_MAC_INTERRUPT -2
96 * enum phy_interface_t - Interface Mode definitions
98 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
100 * @PHY_INTERFACE_MODE_MII: Media-independent interface
101 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
102 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
[all …]
H A Dphylink.h22 MLO_AN_FIXED, /* Fixed-link mode */
23 MLO_AN_INBAND, /* In-band protocol */
26 * PHYLINK_PCS_NEG_NONE - protocol has no inband capability
27 * PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
28 * PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
29 * 1000base-X with autoneg off
30 * PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
32 * PHYLINK_PCS_NEG_INBAND - inband mode selected
33 * PHYLINK_PCS_NEG_ENABLED - negotiation mode enabled
37 PHYLINK_PCS_NEG_OUTBAND = BIT(5),
[all …]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
32 #define MVEBU_COMPHY_SERDES_CFG1_CORE_RESET BIT(5)
42 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5)
69 #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5)
71 #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5)
82 #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5)
108 /* Relative to priv->regmap */
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c125 #include "xgbe-common.h"
149 /* Rate-change complete wait/retry count */
225 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
306 /* Re-driver related definitions */
320 XGBE_PHY_REDRV_MODE_CX = 5,
375 /* Re-driver support */
[all …]
/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_hw.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
38 #define QLC_83XX_MODULE_FIBRE_10GBASE_LRM 0x1 /* 10GBase-LRM */
39 #define QLC_83XX_MODULE_FIBRE_10GBASE_LR 0x2 /* 10GBase-LR */
40 #define QLC_83XX_MODULE_FIBRE_10GBASE_SR 0x3 /* 10GBase-SR */
50 #define QLC_83XX_MODULE_FIBRE_1000BASE_SX 0x7 /* 1000Base-SX */
51 #define QLC_83XX_MODULE_FIBRE_1000BASE_LX 0x8 /* 1000Base-LX */
52 #define QLC_83XX_MODULE_FIBRE_1000BASE_CX 0x9 /* 1000Base-CX */
53 #define QLC_83XX_MODULE_TP_1000BASE_T 0xa /* 1000Base-T*/
77 {QLCNIC_CMD_WRITE_PHY, 5, 1},
[all …]
/linux/drivers/net/usb/
H A Daqc111.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Aquantia Corp. Aquantia AQtion USB to 5GbE Controller
3 * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com>
5 * Copyright (C) 2002-2003 TiVo Inc.
6 * Copyright (C) 2017-2018 ASIX
34 netdev_warn(dev->net, in aqc111_read_cmd_nopm()
35 "Failed to read(0x%x) reg index 0x%04x: %d\n", in aqc111_read_cmd_nopm()
50 netdev_warn(dev->net, in aqc111_read_cmd()
51 "Failed to read(0x%x) reg index 0x%04x: %d\n", in aqc111_read_cmd()
82 int err = -ENOMEM; in __aqc111_write_cmd()
[all …]
H A Dcdc_ether.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2003-2005 by David Brownell
26 return (desc->bInterfaceClass == USB_CLASS_COMM && in is_rndis()
27 desc->bInterfaceSubClass == 2 && in is_rndis()
28 desc->bInterfaceProtocol == 0xff); in is_rndis()
33 return (desc->bInterfaceClass == USB_CLASS_MISC && in is_activesync()
34 desc->bInterfaceSubClass == 1 && in is_activesync()
35 desc->bInterfaceProtocol == 1); in is_activesync()
40 return (desc->bInterfaceClass == USB_CLASS_WIRELESS_CONTROLLER && in is_wireless_rndis()
41 desc->bInterfaceSubClass == 1 && in is_wireless_rndis()
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
161 #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
[all …]
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
[all …]
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_main.c1 // SPDX-License-Identifier: GPL-2.0
76 writel(data, priv->swth_base[0] + offset); in mvpp2_write()
81 return readl(priv->swth_base[0] + offset); in mvpp2_read()
86 return readl_relaxed(priv->swth_base[0] + offset); in mvpp2_read_relaxed()
91 return cpu % priv->nthreads; in mvpp2_cpu_to_thread()
96 writel(data, priv->cm3_base + offset); in mvpp2_cm3_write()
101 return readl(priv->cm3_base + offset); in mvpp2_cm3_read()
124 * - per-thread registers, where each thread has its own copy of the
140 * - global registers that must be accessed through a specific thread
141 * window, because they are related to an access to a per-thread
[all …]
/linux/drivers/net/ethernet/broadcom/bnxt/
H A Dbnxt_ethtool.c1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
50 return bp->msg_enable; in bnxt_get_msglevel()
57 bp->msg_enable = value; in bnxt_set_msglevel()
71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; in bnxt_get_coalesce()
73 hw_coal = &bp->rx_coal; in bnxt_get_coalesce()
74 mult = hw_coal->bufs_per_record; in bnxt_get_coalesce()
75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; in bnxt_get_coalesce()
76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; in bnxt_get_coalesce()
[all …]
H A Dbnxt.c1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
25 #include <linux/dma-mapping.h>
75 #define BNXT_TX_TIMEOUT (5 * HZ)
92 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
93 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
94 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
95 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
97 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_82599.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
65 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599()
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
72 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
74 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
78 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
79 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
[all …]

12