1 // SPDX-License-Identifier: GPL-2.0
5  * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
32 #define     MVEBU_COMPHY_SERDES_CFG1_CORE_RESET	BIT(5)
42 #define     MVEBU_COMPHY_PWRPLL_PHY_MODE(n)	((n) << 5)
69 #define     MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n)	((n) << 5)
71 #define     MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE	BIT(5)
82 #define     MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n)	((n) << 5)
108 /* Relative to priv->regmap */
130  * [ 1- 0]: COMPHY polarity invertion
131  * [ 2- 7]: COMPHY speed
132  * [ 5-11]: COMPHY port index
133  * [12-16]: COMPHY mode
135  * [18-20]: PCIe width (x1, x2, x4)
172 #define COMPHY_FW_MODE_2500BASEX	0x3 /* 2500BASE-X */
204 		.mux = -1,				\
249 	ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),
250 	/* lane 5 */
251 	ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
252 	GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
253 	ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
254 	ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX),
255 	GEN_CONF(5, 2, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
289 		return -EOPNOTSUPP;  in mvebu_comphy_smc()
291 		return -EINVAL;  in mvebu_comphy_smc()
309 		if (conf->lane == lane &&  in mvebu_comphy_get_mode()
310 		    conf->port == port &&  in mvebu_comphy_get_mode()
311 		    conf->mode == mode &&  in mvebu_comphy_get_mode()
312 		    (conf->submode == submode || ignore_submode))  in mvebu_comphy_get_mode()
317 		return -EINVAL;  in mvebu_comphy_get_mode()
320 		return conf->fw_mode;  in mvebu_comphy_get_mode()
322 		return conf->mux;  in mvebu_comphy_get_mode()
339 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_ethernet_init_reset()
342 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);  in mvebu_comphy_ethernet_init_reset()
345 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);  in mvebu_comphy_ethernet_init_reset()
348 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_ethernet_init_reset()
357 	switch (lane->submode) {  in mvebu_comphy_ethernet_init_reset()
378 		dev_err(priv->dev,  in mvebu_comphy_ethernet_init_reset()
380 			lane->submode,  in mvebu_comphy_ethernet_init_reset()
381 			lane->id);  in mvebu_comphy_ethernet_init_reset()
382 		return -ENOTSUPP;  in mvebu_comphy_ethernet_init_reset()
385 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_ethernet_init_reset()
387 	if (lane->submode == PHY_INTERFACE_MODE_RXAUI) {  in mvebu_comphy_ethernet_init_reset()
388 		regmap_read(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, &val);  in mvebu_comphy_ethernet_init_reset()
390 		switch (lane->id) {  in mvebu_comphy_ethernet_init_reset()
396 		case 5:  in mvebu_comphy_ethernet_init_reset()
400 			dev_err(priv->dev,  in mvebu_comphy_ethernet_init_reset()
402 				lane->id);  in mvebu_comphy_ethernet_init_reset()
403 			return -EINVAL;  in mvebu_comphy_ethernet_init_reset()
406 		regmap_write(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, val);  in mvebu_comphy_ethernet_init_reset()
410 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
414 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
416 	/* de-assert reset */  in mvebu_comphy_ethernet_init_reset()
417 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
420 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
426 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);  in mvebu_comphy_ethernet_init_reset()
428 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);  in mvebu_comphy_ethernet_init_reset()
431 	val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));  in mvebu_comphy_ethernet_init_reset()
433 	if (lane->submode == PHY_INTERFACE_MODE_10GBASER)  in mvebu_comphy_ethernet_init_reset()
435 	writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));  in mvebu_comphy_ethernet_init_reset()
438 	val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));  in mvebu_comphy_ethernet_init_reset()
443 	writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));  in mvebu_comphy_ethernet_init_reset()
445 	val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));  in mvebu_comphy_ethernet_init_reset()
448 	writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));  in mvebu_comphy_ethernet_init_reset()
455 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_init_plls()
459 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_init_plls()
463 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_init_plls()
466 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),  in mvebu_comphy_init_plls()
473 		return -ETIMEDOUT;  in mvebu_comphy_init_plls()
476 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
478 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
481 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),  in mvebu_comphy_init_plls()
485 		return -ETIMEDOUT;  in mvebu_comphy_init_plls()
487 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
489 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
497 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_sgmii()
505 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_sgmii()
508 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_sgmii()
510 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_sgmii()
512 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_sgmii()
514 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);  in mvebu_comphy_set_mode_sgmii()
517 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);  in mvebu_comphy_set_mode_sgmii()
519 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_sgmii()
522 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_sgmii()
530 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_rxaui()
538 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_rxaui()
541 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_rxaui()
543 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_rxaui()
545 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_rxaui()
547 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_rxaui()
549 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_rxaui()
551 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_rxaui()
553 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_rxaui()
555 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_rxaui()
558 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_rxaui()
560 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_rxaui()
566 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_rxaui()
568 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_rxaui()
570 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_rxaui()
572 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_rxaui()
575 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_rxaui()
583 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_10gbaser()
591 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
594 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
596 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
598 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
601 	val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
603 	writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
605 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
607 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
610 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_10gbaser()
612 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_10gbaser()
614 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
619 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
621 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
624 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
626 	val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));  in mvebu_comphy_set_mode_10gbaser()
629 	writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));  in mvebu_comphy_set_mode_10gbaser()
632 	val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
636 	writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
638 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
640 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
642 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
652 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
654 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_10gbaser()
656 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_10gbaser()
658 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_10gbaser()
661 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_10gbaser()
663 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
665 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
668 	val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
671 	writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
674 	val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
676 	writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
678 	val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
681 	writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
683 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
685 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
687 	val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
690 	writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
692 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
695 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
697 	val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));  in mvebu_comphy_set_mode_10gbaser()
699 	writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));  in mvebu_comphy_set_mode_10gbaser()
701 	val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
703 	writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
705 	val = readl(priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
709 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
711 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
714 	val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
717 	writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
725 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_on_legacy()
729 	mux = mvebu_comphy_get_mux(lane->id, lane->port,  in mvebu_comphy_power_on_legacy()
730 				   lane->mode, lane->submode);  in mvebu_comphy_power_on_legacy()
732 		return -ENOTSUPP;  in mvebu_comphy_power_on_legacy()
734 	regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);  in mvebu_comphy_power_on_legacy()
735 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));  in mvebu_comphy_power_on_legacy()
736 	regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);  in mvebu_comphy_power_on_legacy()
738 	regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);  in mvebu_comphy_power_on_legacy()
739 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));  in mvebu_comphy_power_on_legacy()
740 	val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);  in mvebu_comphy_power_on_legacy()
741 	regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);  in mvebu_comphy_power_on_legacy()
743 	switch (lane->submode) {  in mvebu_comphy_power_on_legacy()
755 		return -ENOTSUPP;  in mvebu_comphy_power_on_legacy()
759 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_on_legacy()
761 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_on_legacy()
769 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_on()
774 	fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,  in mvebu_comphy_power_on()
775 					   lane->mode, lane->submode);  in mvebu_comphy_power_on()
780 	switch (lane->mode) {  in mvebu_comphy_power_on()
782 		switch (lane->submode) {  in mvebu_comphy_power_on()
784 			dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",  in mvebu_comphy_power_on()
785 				lane->id);  in mvebu_comphy_power_on()
789 			dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",  in mvebu_comphy_power_on()
790 				lane->id);  in mvebu_comphy_power_on()
794 			dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",  in mvebu_comphy_power_on()
795 				lane->id);  in mvebu_comphy_power_on()
799 			dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",  in mvebu_comphy_power_on()
800 				lane->id);  in mvebu_comphy_power_on()
804 			dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",  in mvebu_comphy_power_on()
805 				lane->id);  in mvebu_comphy_power_on()
809 			dev_err(priv->dev, "unsupported Ethernet mode (%d)\n",  in mvebu_comphy_power_on()
810 				lane->submode);  in mvebu_comphy_power_on()
811 			return -ENOTSUPP;  in mvebu_comphy_power_on()
813 		fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);  in mvebu_comphy_power_on()
817 		dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);  in mvebu_comphy_power_on()
818 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);  in mvebu_comphy_power_on()
821 		dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);  in mvebu_comphy_power_on()
822 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);  in mvebu_comphy_power_on()
825 		dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,  in mvebu_comphy_power_on()
826 			lane->submode);  in mvebu_comphy_power_on()
827 		fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,  in mvebu_comphy_power_on()
828 						lane->submode);  in mvebu_comphy_power_on()
831 		dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);  in mvebu_comphy_power_on()
832 		return -ENOTSUPP;  in mvebu_comphy_power_on()
835 	ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,  in mvebu_comphy_power_on()
840 	if (ret == -EOPNOTSUPP)  in mvebu_comphy_power_on()
841 		dev_err(priv->dev,  in mvebu_comphy_power_on()
844 	dev_warn(priv->dev,  in mvebu_comphy_power_on()
846 		 lane->id, lane->mode, ret);  in mvebu_comphy_power_on()
861 	if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)  in mvebu_comphy_set_mode()
862 		return -EINVAL;  in mvebu_comphy_set_mode()
864 	lane->mode = mode;  in mvebu_comphy_set_mode()
865 	lane->submode = submode;  in mvebu_comphy_set_mode()
868 	if (mode == PHY_MODE_PCIE && !lane->submode)  in mvebu_comphy_set_mode()
869 		lane->submode = 1;  in mvebu_comphy_set_mode()
877 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_off_legacy()
880 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_off_legacy()
884 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_off_legacy()
886 	regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);  in mvebu_comphy_power_off_legacy()
887 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));  in mvebu_comphy_power_off_legacy()
888 	regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);  in mvebu_comphy_power_off_legacy()
890 	regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);  in mvebu_comphy_power_off_legacy()
891 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));  in mvebu_comphy_power_off_legacy()
892 	regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);  in mvebu_comphy_power_off_legacy()
900 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_off()
903 	ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys,  in mvebu_comphy_power_off()
904 			       lane->id, 0);  in mvebu_comphy_power_off()
925 	if (WARN_ON(args->args[0] >= MVEBU_COMPHY_PORTS))  in mvebu_comphy_xlate()
926 		return ERR_PTR(-EINVAL);  in mvebu_comphy_xlate()
933 	lane->port = args->args[0];  in mvebu_comphy_xlate()
942 	priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk");  in mvebu_comphy_init_clks()
943 	if (IS_ERR(priv->mg_domain_clk))  in mvebu_comphy_init_clks()
944 		return PTR_ERR(priv->mg_domain_clk);  in mvebu_comphy_init_clks()
946 	ret = clk_prepare_enable(priv->mg_domain_clk);  in mvebu_comphy_init_clks()
950 	priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk");  in mvebu_comphy_init_clks()
951 	if (IS_ERR(priv->mg_core_clk)) {  in mvebu_comphy_init_clks()
952 		ret = PTR_ERR(priv->mg_core_clk);  in mvebu_comphy_init_clks()
956 	ret = clk_prepare_enable(priv->mg_core_clk);  in mvebu_comphy_init_clks()
960 	priv->axi_clk = devm_clk_get(priv->dev, "axi_clk");  in mvebu_comphy_init_clks()
961 	if (IS_ERR(priv->axi_clk)) {  in mvebu_comphy_init_clks()
962 		ret = PTR_ERR(priv->axi_clk);  in mvebu_comphy_init_clks()
966 	ret = clk_prepare_enable(priv->axi_clk);  in mvebu_comphy_init_clks()
973 	clk_disable_unprepare(priv->mg_core_clk);  in mvebu_comphy_init_clks()
976 	clk_disable_unprepare(priv->mg_domain_clk);  in mvebu_comphy_init_clks()
978 	priv->mg_domain_clk = NULL;  in mvebu_comphy_init_clks()
979 	priv->mg_core_clk = NULL;  in mvebu_comphy_init_clks()
980 	priv->axi_clk = NULL;  in mvebu_comphy_init_clks()
987 	if (priv->axi_clk)  in mvebu_comphy_disable_unprepare_clks()
988 		clk_disable_unprepare(priv->axi_clk);  in mvebu_comphy_disable_unprepare_clks()
990 	if (priv->mg_core_clk)  in mvebu_comphy_disable_unprepare_clks()
991 		clk_disable_unprepare(priv->mg_core_clk);  in mvebu_comphy_disable_unprepare_clks()
993 	if (priv->mg_domain_clk)  in mvebu_comphy_disable_unprepare_clks()
994 		clk_disable_unprepare(priv->mg_domain_clk);  in mvebu_comphy_disable_unprepare_clks()
1005 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in mvebu_comphy_probe()
1007 		return -ENOMEM;  in mvebu_comphy_probe()
1009 	priv->dev = &pdev->dev;  in mvebu_comphy_probe()
1010 	priv->regmap =  in mvebu_comphy_probe()
1011 		syscon_regmap_lookup_by_phandle(pdev->dev.of_node,  in mvebu_comphy_probe()
1012 						"marvell,system-controller");  in mvebu_comphy_probe()
1013 	if (IS_ERR(priv->regmap))  in mvebu_comphy_probe()
1014 		return PTR_ERR(priv->regmap);  in mvebu_comphy_probe()
1015 	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in mvebu_comphy_probe()
1016 	if (IS_ERR(priv->base))  in mvebu_comphy_probe()
1017 		return PTR_ERR(priv->base);  in mvebu_comphy_probe()
1025 		if (ret == -EPROBE_DEFER)  in mvebu_comphy_probe()
1027 		dev_warn(&pdev->dev, "cannot initialize clocks\n");  in mvebu_comphy_probe()
1034 	priv->cp_phys = res->start;  in mvebu_comphy_probe()
1036 	for_each_available_child_of_node(pdev->dev.of_node, child) {  in mvebu_comphy_probe()
1043 			dev_err(&pdev->dev, "missing 'reg' property (%d)\n",  in mvebu_comphy_probe()
1049 			dev_err(&pdev->dev, "invalid 'reg' property\n");  in mvebu_comphy_probe()
1053 		lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);  in mvebu_comphy_probe()
1056 			ret = -ENOMEM;  in mvebu_comphy_probe()
1060 		phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops);  in mvebu_comphy_probe()
1067 		lane->priv = priv;  in mvebu_comphy_probe()
1068 		lane->mode = PHY_MODE_INVALID;  in mvebu_comphy_probe()
1069 		lane->submode = PHY_INTERFACE_MODE_NA;  in mvebu_comphy_probe()
1070 		lane->id = val;  in mvebu_comphy_probe()
1071 		lane->port = -1;  in mvebu_comphy_probe()
1078 		 * reasons we cannot de-configure the COMPHY without being sure  in mvebu_comphy_probe()
1079 		 * that the firmware is up-to-date and fully-featured.  in mvebu_comphy_probe()
1083 	dev_set_drvdata(&pdev->dev, priv);  in mvebu_comphy_probe()
1084 	provider = devm_of_phy_provider_register(&pdev->dev,  in mvebu_comphy_probe()
1096 	{ .compatible = "marvell,comphy-cp110" },
1104 		.name = "mvebu-comphy",
1110 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");