Lines Matching +full:5 +full:gbase +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
65 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599()
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
72 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
74 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
78 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
79 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
83 if (hw->phy.multispeed_fiber) { in ixgbe_init_mac_link_ops_82599()
85 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
86 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; in ixgbe_init_mac_link_ops_82599()
87 mac->ops.set_rate_select_speed = in ixgbe_init_mac_link_ops_82599()
90 if ((mac->ops.get_media_type(hw) == in ixgbe_init_mac_link_ops_82599()
92 (hw->phy.smart_speed == ixgbe_smart_speed_auto || in ixgbe_init_mac_link_ops_82599()
93 hw->phy.smart_speed == ixgbe_smart_speed_on) && in ixgbe_init_mac_link_ops_82599()
95 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; in ixgbe_init_mac_link_ops_82599()
97 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; in ixgbe_init_mac_link_ops_82599()
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { in ixgbe_setup_sfp_modules_82599()
109 hw->phy.ops.reset = NULL; in ixgbe_setup_sfp_modules_82599()
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in ixgbe_setup_sfp_modules_82599()
120 return -EBUSY; in ixgbe_setup_sfp_modules_82599()
122 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) in ixgbe_setup_sfp_modules_82599()
127 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) in ixgbe_setup_sfp_modules_82599()
132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_setup_sfp_modules_82599()
137 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_setup_sfp_modules_82599()
138 hw->eeprom.semaphore_delay * 2000); in ixgbe_setup_sfp_modules_82599()
141 ret_val = hw->mac.ops.prot_autoc_write(hw, in ixgbe_setup_sfp_modules_82599()
142 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, in ixgbe_setup_sfp_modules_82599()
147 return -EIO; in ixgbe_setup_sfp_modules_82599()
155 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_setup_sfp_modules_82599()
159 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_setup_sfp_modules_82599()
160 hw->eeprom.semaphore_delay * 2000); in ixgbe_setup_sfp_modules_82599()
162 return -EIO; in ixgbe_setup_sfp_modules_82599()
166 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
171 * For this part (82599) we need to wrap read-modify-writes with a possible
184 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in prot_autoc_read_82599()
187 return -EBUSY; in prot_autoc_read_82599()
197 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
215 * - We didn't do it already (in the read part of a read-modify-write) in prot_autoc_write_82599()
216 * - LESM is enabled. in prot_autoc_write_82599()
219 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in prot_autoc_write_82599()
222 return -EBUSY; in prot_autoc_write_82599()
235 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in prot_autoc_write_82599()
242 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_82599()
246 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; in ixgbe_get_invariants_82599()
247 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; in ixgbe_get_invariants_82599()
248 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; in ixgbe_get_invariants_82599()
249 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; in ixgbe_get_invariants_82599()
250 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; in ixgbe_get_invariants_82599()
251 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; in ixgbe_get_invariants_82599()
252 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); in ixgbe_get_invariants_82599()
258 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
268 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_phy_ops_82599()
269 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82599()
273 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { in ixgbe_init_phy_ops_82599()
275 hw->phy.qsfp_shared_i2c_bus = true; in ixgbe_init_phy_ops_82599()
287 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
288 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
292 ret_val = phy->ops.identify(hw); in ixgbe_init_phy_ops_82599()
298 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { in ixgbe_init_phy_ops_82599()
299 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; in ixgbe_init_phy_ops_82599()
300 mac->ops.get_link_capabilities = in ixgbe_init_phy_ops_82599()
305 switch (hw->phy.type) { in ixgbe_init_phy_ops_82599()
307 phy->ops.check_link = &ixgbe_check_phy_link_tnx; in ixgbe_init_phy_ops_82599()
308 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; in ixgbe_init_phy_ops_82599()
318 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
332 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || in ixgbe_get_link_capabilities_82599()
333 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || in ixgbe_get_link_capabilities_82599()
334 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || in ixgbe_get_link_capabilities_82599()
335 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || in ixgbe_get_link_capabilities_82599()
336 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || in ixgbe_get_link_capabilities_82599()
337 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || in ixgbe_get_link_capabilities_82599()
338 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || in ixgbe_get_link_capabilities_82599()
339 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1) { in ixgbe_get_link_capabilities_82599()
350 if (hw->mac.orig_link_settings_stored) in ixgbe_get_link_capabilities_82599()
351 autoc = hw->mac.orig_autoc; in ixgbe_get_link_capabilities_82599()
405 return -EIO; in ixgbe_get_link_capabilities_82599()
408 if (hw->phy.multispeed_fiber) { in ixgbe_get_link_capabilities_82599()
412 /* QSFP must not enable auto-negotiation */ in ixgbe_get_link_capabilities_82599()
413 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) in ixgbe_get_link_capabilities_82599()
423 * ixgbe_get_media_type_82599 - Get media type
431 switch (hw->phy.type) { in ixgbe_get_media_type_82599()
440 switch (hw->device_id) { in ixgbe_get_media_type_82599()
476 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
487 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); in ixgbe_stop_mac_link_on_d3_82599()
489 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && in ixgbe_stop_mac_link_on_d3_82599()
498 * ixgbe_start_mac_link_82599 - Setup MAC link settings
515 status = hw->mac.ops.acquire_swfw_sync(hw, in ixgbe_start_mac_link_82599()
527 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_start_mac_link_82599()
546 status = -EIO; in ixgbe_start_mac_link_82599()
559 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
582 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
601 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
607 * so, we set the speed then disable and re-enable the tx laser, to
618 if (hw->mac.autotry_restart) { in ixgbe_flap_tx_laser_multispeed_fiber()
621 hw->mac.autotry_restart = false; in ixgbe_flap_tx_laser_multispeed_fiber()
626 * ixgbe_set_hard_rate_select_speed - Set module link speed
655 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
673 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_smartspeed()
676 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_smartspeed()
679 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_smartspeed()
682 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; in ixgbe_setup_mac_link_smartspeed()
692 hw->phy.smart_speed_active = false; in ixgbe_setup_mac_link_smartspeed()
705 for (i = 0; i < 5; i++) { in ixgbe_setup_mac_link_smartspeed()
709 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_smartspeed()
728 hw->phy.smart_speed_active = true; in ixgbe_setup_mac_link_smartspeed()
738 * connect attempts as defined in the AN MAS table 73-7. in ixgbe_setup_mac_link_smartspeed()
744 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_smartspeed()
754 hw->phy.smart_speed_active = false; in ixgbe_setup_mac_link_smartspeed()
765 * ixgbe_setup_mac_link_82599 - Set MAC link speed
792 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, in ixgbe_setup_mac_link_82599()
800 return -EINVAL; in ixgbe_setup_mac_link_82599()
803 if (hw->mac.orig_link_settings_stored) in ixgbe_setup_mac_link_82599()
804 orig_autoc = hw->mac.orig_autoc; in ixgbe_setup_mac_link_82599()
820 (hw->phy.smart_speed_active == false)) in ixgbe_setup_mac_link_82599()
849 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); in ixgbe_setup_mac_link_82599()
867 status = -EIO; in ixgbe_setup_mac_link_82599()
881 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
895 status = hw->phy.ops.setup_link_speed(hw, speed, in ixgbe_setup_copper_link_82599()
904 * ixgbe_reset_hw_82599 - Perform hardware reset
920 status = hw->mac.ops.stop_adapter(hw); in ixgbe_reset_hw_82599()
930 status = hw->phy.ops.init(hw); in ixgbe_reset_hw_82599()
932 if (status == -EOPNOTSUPP) in ixgbe_reset_hw_82599()
936 if (hw->phy.sfp_setup_needed) { in ixgbe_reset_hw_82599()
937 status = hw->mac.ops.setup_sfp(hw); in ixgbe_reset_hw_82599()
938 hw->phy.sfp_setup_needed = false; in ixgbe_reset_hw_82599()
941 if (status == -EOPNOTSUPP) in ixgbe_reset_hw_82599()
945 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) in ixgbe_reset_hw_82599()
946 hw->phy.ops.reset(hw); in ixgbe_reset_hw_82599()
959 if (!hw->force_full_reset) { in ixgbe_reset_hw_82599()
960 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); in ixgbe_reset_hw_82599()
970 /* Poll for reset bit to self-clear indicating reset is complete */ in ixgbe_reset_hw_82599()
979 status = -EIO; in ixgbe_reset_hw_82599()
990 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { in ixgbe_reset_hw_82599()
991 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_reset_hw_82599()
1010 if (hw->mac.orig_link_settings_stored == false) { in ixgbe_reset_hw_82599()
1011 hw->mac.orig_autoc = autoc; in ixgbe_reset_hw_82599()
1012 hw->mac.orig_autoc2 = autoc2; in ixgbe_reset_hw_82599()
1013 hw->mac.orig_link_settings_stored = true; in ixgbe_reset_hw_82599()
1016 /* If MNG FW is running on a multi-speed device that in ixgbe_reset_hw_82599()
1022 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || in ixgbe_reset_hw_82599()
1023 hw->wol_enabled) in ixgbe_reset_hw_82599()
1024 hw->mac.orig_autoc = in ixgbe_reset_hw_82599()
1025 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | in ixgbe_reset_hw_82599()
1028 if (autoc != hw->mac.orig_autoc) { in ixgbe_reset_hw_82599()
1029 status = hw->mac.ops.prot_autoc_write(hw, in ixgbe_reset_hw_82599()
1030 hw->mac.orig_autoc, in ixgbe_reset_hw_82599()
1037 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { in ixgbe_reset_hw_82599()
1039 autoc2 |= (hw->mac.orig_autoc2 & in ixgbe_reset_hw_82599()
1046 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_82599()
1053 hw->mac.num_rar_entries = IXGBE_82599_RAR_ENTRIES; in ixgbe_reset_hw_82599()
1054 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_82599()
1057 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); in ixgbe_reset_hw_82599()
1060 if (is_valid_ether_addr(hw->mac.san_addr)) { in ixgbe_reset_hw_82599()
1062 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; in ixgbe_reset_hw_82599()
1064 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_82599()
1065 hw->mac.san_addr, 0, IXGBE_RAH_AV); in ixgbe_reset_hw_82599()
1068 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_82599()
1072 hw->mac.num_rar_entries--; in ixgbe_reset_hw_82599()
1076 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, in ixgbe_reset_hw_82599()
1077 &hw->mac.wwpn_prefix); in ixgbe_reset_hw_82599()
1083 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1098 return -EIO; in ixgbe_fdir_check_cmd_complete()
1102 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1120 …hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); in ixgbe_reinit_fdir_tables_82599()
1129 * before re-writing the FDIRCTRL control register with the same value. in ixgbe_reinit_fdir_tables_82599()
1130 * - write 1 to bit 8 of FDIRCMD register & in ixgbe_reinit_fdir_tables_82599()
1131 * - write 0 to bit 8 of FDIRCMD register in ixgbe_reinit_fdir_tables_82599()
1151 /* Poll init-done after we write FDIRCTRL register */ in ixgbe_reinit_fdir_tables_82599()
1160 return -EIO; in ixgbe_reinit_fdir_tables_82599()
1174 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1187 * Poll init-done after we write the register. Estimated times: in ixgbe_fdir_enable_82599()
1213 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1222 * Move the flexible bytes to use the ethertype - shift 6 words in ixgbe_init_fdir_signature_82599()
1237 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1248 * Move the flexible bytes to use the ethertype - shift 6 words in ixgbe_init_fdir_perfect_82599()
1279 sig_hash ^= lo_hash_dword << (16 - n); \
1285 sig_hash ^= hi_hash_dword << (16 - n); \
1289 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1332 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); in ixgbe_atr_compute_sig_hash_82599()
1356 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter
1381 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); in ixgbe_fdir_add_signature_filter_82599()
1392 return -EIO; in ixgbe_fdir_add_signature_filter_82599()
1404 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits in ixgbe_fdir_add_signature_filter_82599()
1405 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. in ixgbe_fdir_add_signature_filter_82599()
1411 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); in ixgbe_fdir_add_signature_filter_82599()
1426 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1447 input->dword_stream[i] &= input_mask->dword_stream[i]; in ixgbe_atr_compute_perfect_hash_82599()
1450 flow_vm_vlan = ntohl(input->dword_stream[0]); in ixgbe_atr_compute_perfect_hash_82599()
1454 hi_dword ^= input->dword_stream[i]; in ixgbe_atr_compute_perfect_hash_82599()
1481 input->formatted.bkt_hash = (__force __be16)(bucket_hash & 0x1FFF); in ixgbe_atr_compute_perfect_hash_82599()
1485 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1495 u32 mask = ntohs(input_mask->formatted.dst_port); in ixgbe_get_fdirtcpm_82599()
1498 mask |= ntohs(input_mask->formatted.src_port); in ixgbe_get_fdirtcpm_82599()
1507 * that are either all or in part big-endian. As a result on big-endian
1508 * systems we will end up byte swapping the value to little-endian before
1510 * big-endian format.
1539 if (input_mask->formatted.bkt_hash) in ixgbe_fdir_set_input_mask_82599()
1543 switch (input_mask->formatted.vm_pool & 0x7F) { in ixgbe_fdir_set_input_mask_82599()
1551 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1554 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { in ixgbe_fdir_set_input_mask_82599()
1557 if (input_mask->formatted.dst_port || in ixgbe_fdir_set_input_mask_82599()
1558 input_mask->formatted.src_port) { in ixgbe_fdir_set_input_mask_82599()
1560 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1567 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1570 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { in ixgbe_fdir_set_input_mask_82599()
1588 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1591 switch ((__force u16)input_mask->formatted.flex_bytes & 0xFFFF) { in ixgbe_fdir_set_input_mask_82599()
1600 return -EIO; in ixgbe_fdir_set_input_mask_82599()
1603 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ in ixgbe_fdir_set_input_mask_82599()
1614 switch (hw->mac.type) { in ixgbe_fdir_set_input_mask_82599()
1624 /* store source and destination IP masks (big-enian) */ in ixgbe_fdir_set_input_mask_82599()
1626 ~input_mask->formatted.src_ip[0]); in ixgbe_fdir_set_input_mask_82599()
1628 ~input_mask->formatted.dst_ip[0]); in ixgbe_fdir_set_input_mask_82599()
1642 input->formatted.src_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1644 input->formatted.src_ip[1]); in ixgbe_fdir_write_perfect_filter_82599()
1646 input->formatted.src_ip[2]); in ixgbe_fdir_write_perfect_filter_82599()
1648 /* record the source address (big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1649 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1651 /* record the first 32 bits of the destination address (big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1654 /* record source and destination port (little-endian)*/ in ixgbe_fdir_write_perfect_filter_82599()
1655 fdirport = be16_to_cpu(input->formatted.dst_port); in ixgbe_fdir_write_perfect_filter_82599()
1657 fdirport |= be16_to_cpu(input->formatted.src_port); in ixgbe_fdir_write_perfect_filter_82599()
1660 /* record vlan (little-endian) and flex_bytes(big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1661 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); in ixgbe_fdir_write_perfect_filter_82599()
1663 fdirvlan |= ntohs(input->formatted.vlan_id); in ixgbe_fdir_write_perfect_filter_82599()
1667 fdirhash = (__force u32)input->formatted.bkt_hash; in ixgbe_fdir_write_perfect_filter_82599()
1682 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; in ixgbe_fdir_write_perfect_filter_82599()
1684 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; in ixgbe_fdir_write_perfect_filter_82599()
1705 fdirhash = (__force u32)input->formatted.bkt_hash; in ixgbe_fdir_erase_perfect_filter_82599()
1733 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1755 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1775 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1780 * Then performs revision-specific operations, if any.
1795 hw->mac.autotry_restart = true; in ixgbe_start_hw_82599()
1801 * ixgbe_identify_phy_82599 - Get physical layer module
1812 /* Detect PHY if not unknown - returns success if already detected. */ in ixgbe_identify_phy_82599()
1815 /* 82599 10GBASE-T requires an external PHY */ in ixgbe_identify_phy_82599()
1816 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) in ixgbe_identify_phy_82599()
1822 if (hw->phy.type == ixgbe_phy_unknown) { in ixgbe_identify_phy_82599()
1823 hw->phy.type = ixgbe_phy_none; in ixgbe_identify_phy_82599()
1828 if (hw->phy.type == ixgbe_phy_sfp_unsupported) in ixgbe_identify_phy_82599()
1829 return -EOPNOTSUPP; in ixgbe_identify_phy_82599()
1835 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1849 hw->mac.ops.disable_rx_buff(hw); in ixgbe_enable_rx_dma_82599()
1852 hw->mac.ops.enable_rx(hw); in ixgbe_enable_rx_dma_82599()
1854 hw->mac.ops.disable_rx(hw); in ixgbe_enable_rx_dma_82599()
1856 hw->mac.ops.enable_rx_buff(hw); in ixgbe_enable_rx_dma_82599()
1862 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1868 * Return: -EACCES if the FW is not present or if the FW version is
1874 int status = -EACCES; in ixgbe_verify_fw_version_82599()
1879 if (hw->phy.media_type != ixgbe_media_type_fiber) in ixgbe_verify_fw_version_82599()
1884 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) in ixgbe_verify_fw_version_82599()
1888 return -EACCES; in ixgbe_verify_fw_version_82599()
1892 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) in ixgbe_verify_fw_version_82599()
1896 return -EACCES; in ixgbe_verify_fw_version_82599()
1900 if (hw->eeprom.ops.read(hw, offset, &fw_version)) in ixgbe_verify_fw_version_82599()
1910 return -EACCES; in ixgbe_verify_fw_version_82599()
1914 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1926 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); in ixgbe_verify_lesm_fw_enabled_82599()
1932 status = hw->eeprom.ops.read(hw, (fw_offset + in ixgbe_verify_lesm_fw_enabled_82599()
1941 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + in ixgbe_verify_lesm_fw_enabled_82599()
1952 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
1965 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_read_eeprom_buffer_82599()
1970 if (eeprom->type == ixgbe_eeprom_spi && in ixgbe_read_eeprom_buffer_82599()
1971 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR) in ixgbe_read_eeprom_buffer_82599()
1979 * ixgbe_read_eeprom_82599 - Read EEPROM word using
1991 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_read_eeprom_82599()
1997 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR) in ixgbe_read_eeprom_82599()
2004 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2009 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2043 ret_val = -EIO; in ixgbe_reset_pipeline_82599()
2058 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2074 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_read_i2c_byte_82599()
2087 timeout--; in ixgbe_read_i2c_byte_82599()
2092 status = -EIO; in ixgbe_read_i2c_byte_82599()
2100 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_read_i2c_byte_82599()
2112 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2128 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_write_i2c_byte_82599()
2141 timeout--; in ixgbe_write_i2c_byte_82599()
2146 status = -EIO; in ixgbe_write_i2c_byte_82599()
2154 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_write_i2c_byte_82599()