Lines Matching +full:5 +full:gbase +full:- +full:x
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9132-sr-cex7.dtsi"
19 compatible = "solidrun,cn9132-clearfog",
20 "solidrun,cn9132-sr-cex7", "marvell,cn9130";
32 gpio-keys {
33 compatible = "gpio-keys";
34 pinctrl-names = "default";
35 pinctrl-0 = <&cp1_wake0_pins>;
37 button-0 {
40 linux,can-disable;
46 compatible = "gpio-leds";
47 pinctrl-names = "default";
48 pinctrl-0 = <&cp1_batlow_pins &cp2_rsvd4_pins>;
51 led-io-0 {
54 function-enumerator = <0>;
55 default-state = "off";
60 led-io-1 {
63 function-enumerator = <1>;
64 default-state = "off";
70 rfkill-m2-wlan {
71 compatible = "rfkill-gpio";
73 radio-type = "wlan";
74 pinctrl-names = "default";
75 pinctrl-0 = <&cp1_10g_phy_rst_01_pins>;
76 /* rfkill-gpio inverts internally */
77 shutdown-gpios = <&cp1_gpio2 11 GPIO_ACTIVE_HIGH>;
81 rfkill-m2-wlan {
82 compatible = "rfkill-gpio";
84 radio-type = "wlan";
85 pinctrl-names = "default";
86 pinctrl-0 = <&cp1_10g_phy_rst_23_pins>;
87 /* rfkill-gpio inverts internally */
88 shutdown-gpios = <&cp1_gpio2 10 GPIO_ACTIVE_HIGH>;
92 rfkill-m2-wwan {
93 compatible = "rfkill-gpio";
95 radio-type = "wwan";
96 pinctrl-names = "default";
97 pinctrl-0 = <&cp2_rsvd3_pins>;
98 /* rfkill-gpio inverts internally */
99 shutdown-gpios = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
103 rfkill-m2-gnss {
104 compatible = "rfkill-gpio";
106 radio-type = "gps";
107 pinctrl-names = "default";
108 pinctrl-0 = <&cp2_rsvd8_pins>;
109 /* rfkill-gpio inverts internally */
110 shutdown-gpios = <&cp2_gpio1 8 GPIO_ACTIVE_HIGH>;
114 rfkill-mpcie-wlan {
115 compatible = "rfkill-gpio";
117 radio-type = "wlan";
118 pinctrl-names = "default";
119 pinctrl-0 = <&cp2_rsvd2_pins>;
120 /* rfkill-gpio inverts internally */
121 shutdown-gpios = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
126 i2c-bus = <&com_10g_sfp_i2c0>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&com_10g_int0_pins>;
129 mod-def0-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
130 maximum-power-milliwatt = <2000>;
137 power-sensor@40 {
140 #io-channel-cells = <1>;
142 shunt-resistor = <2000>;
148 #address-cells = <1>;
149 #size-cells = <0>;
161 * - LED[0]: link is 1000Mbps: On (yellow): 0111
162 * - LED[1]: link/activity: On/Blink (green): 0001
163 * - LED[2]: Off (green): 1000
165 marvell,reg-init = <3 16 0xf000 0x0817>;
168 #address-cells = <1>;
169 #size-cells = <0>;
176 default-state = "keep";
184 default-state = "keep";
192 default-state = "keep";
197 /* SRDS #4 - 10GE */
200 phy-mode = "10gbase-r";
201 managed = "in-band-status";
207 phy-mode = "2500base-x";
211 fixed-link {
213 full-duplex;
224 i2c-mux@77 {
245 carrier_mpcie_i2c: i2c@5 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 reg = <5>;
250 /* Routed to mini-PCIe (J14) */
254 #address-cells = <1>;
255 #size-cells = <0>;
264 ethernet-switch@4 {
269 #address-cells = <1>;
270 #size-cells = <0>;
272 sw_phy1: ethernet-phy@1 {
276 sw_phy2: ethernet-phy@2 {
280 sw_phy3: ethernet-phy@3 {
284 sw_phy4: ethernet-phy@4 {
289 ethernet-ports {
290 #address-cells = <1>;
291 #size-cells = <0>;
293 ethernet-port@1 {
296 phy-handle = <&sw_phy1>;
297 phy-mode = "internal";
300 #address-cells = <1>;
301 #size-cells = <0>;
307 default-state = "keep";
314 default-state = "keep";
319 ethernet-port@2 {
322 phy-handle = <&sw_phy2>;
323 phy-mode = "internal";
326 #address-cells = <1>;
327 #size-cells = <0>;
333 default-state = "keep";
340 default-state = "keep";
345 ethernet-port@3 {
348 phy-handle = <&sw_phy3>;
349 phy-mode = "internal";
352 #address-cells = <1>;
353 #size-cells = <0>;
359 default-state = "keep";
366 default-state = "keep";
371 ethernet-port@4 {
374 phy-handle = <&sw_phy4>;
375 phy-mode = "internal";
378 #address-cells = <1>;
379 #size-cells = <0>;
385 default-state = "keep";
392 default-state = "keep";
397 ethernet-port@5 {
398 reg = <5>;
401 phy-mode = "2500base-x";
403 fixed-link {
405 full-duplex;
413 /* SRDS #0,#1,#2,#3 - PCIe */
415 num-lanes = <4>;
423 * - J7-10: PWRBTN
425 pinctrl-names = "default";
426 pinctrl-0 = <&cp0_pwrbtn_pins>;
431 pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mmc0_cd_pins>;
432 pinctrl-names = "default";
433 bus-width = <4>;
434 no-1-8-v;
440 pinctrl-0 = <&cp0_spi1_pins>, <&cp0_spi1_cs1_pins>;
443 compatible = "jedec,spi-nor";
446 spi-max-frequency = <50000000>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&cp0_uart2_pins>;
458 /* M.2 "CON5" swaps D+/D- */
459 swap-dx-lanes = <1>;
466 /* SRDS #2 - 5GE */
469 phy-mode = "5gbase-r";
471 managed = "in-band-status";
475 /* SRDS #0,#1 - PCIe */
477 num-lanes = <2>;
482 /* SRDS #4 - PCIe */
484 num-lanes = <1>;
489 /* SRDS #5 - PCIe */
491 num-lanes = <1>;
499 * - J7-8: RSVD16
500 * - J7-10: THRM
501 * - J10-1: WAKE1
502 * - J10-2: SATA_ACT
503 * - J10-8: THERMTRIP
505 pinctrl-names = "default";
506 pinctrl-0 = <&cp1_rsvd16_pins &cp1_sata_act_pins &cp1_thrm_irq_pins>,
510 /* SRDS #3 - SATA */
515 /delete-node/ sata-port@0;
517 sata-port@1 {
523 /* M.2 "CON4" swaps D+/D- */
524 swap-dx-lanes = <0>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&cp1_xmdio_pins>;
532 cp1_eth_phy0: ethernet-phy@8 {
533 compatible = "ethernet-phy-ieee802.3-c45";
535 pinctrl-names = "default";
536 pinctrl-0 = <&com_10g_int1_pins>;
537 interrupt-parent = <&cp1_gpio2>;
541 #address-cells = <1>;
542 #size-cells = <0>;
548 default-state = "keep";
555 default-state = "keep";
565 /* SRDS #2 - 5GE */
568 phy-mode = "5gbase-r";
570 managed = "in-band-status";
575 pinctrl-names= "default";
576 pinctrl-0 = <&cp2_rsvd9_pins>;
579 m2-wwan-reset-hog {
580 gpio-hog;
582 output-low;
583 line-name = "m2-wwan-reset";
587 /* SRDS #0 - PCIe */
589 num-lanes = <1>;
594 /* SRDS #4 - PCIe */
596 num-lanes = <1>;
601 /* SRDS #5 - PCIe */
603 num-lanes = <1>;
611 * - J7-1: RSVD10
612 * - J7-3: RSVD11
613 * - J7-5: RSVD56
614 * - J7-6: RSVD7
615 * - J7-7: RSVD27
616 * - J10-3: RSVD31
617 * - J10-5: RSVD5
618 * - J10-6: RSVD32
619 * - J10-7: RSVD0
620 * - J10-9: RSVD1
622 pinctrl-names = "default";
623 pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd1_pins &cp2_rsvd5_pins>,
629 /* SRDS #3 - SATA */
634 /delete-node/ sata-port@0;
636 sata-port@1 {
642 pinctrl-names = "default";
643 pinctrl-0 = <&cp2_xmdio_pins>;
646 cp2_eth_phy0: ethernet-phy@8 {
647 compatible = "ethernet-phy-ieee802.3-c45";
649 pinctrl-names = "default";
650 pinctrl-0 = <&com_10g_int2_pins>;
651 interrupt-parent = <&cp2_gpio2>;
655 #address-cells = <1>;
656 #size-cells = <0>;
662 default-state = "keep";
669 default-state = "keep";