Lines Matching +full:5 +full:gbase +full:- +full:x
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
38 - description: GOP clock
39 - description: MG clock
40 - description: MG Core clock
41 - description: AXI clock
43 clock-names:
46 - const: pp_clk
47 - const: gop_clk
48 - const: mg_clk
49 - const: mg_core_clk
50 - const: axi_clk
52 dma-coherent: true
54 marvell,system-controller:
59 '^(ethernet-)?port@[0-2]$':
62 $ref: ethernet-controller.yaml#
75 interrupt-names:
78 - const: hif0
79 - const: hif1
80 - const: hif2
81 - const: hif3
82 - const: hif4
83 - const: hif5
84 - const: hif6
85 - const: hif7
86 - const: hif8
87 - const: link
92 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
93 "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
104 phy-mode:
106 - gmii
107 - sgmii
108 - rgmii-id
109 - 1000base-x
110 - 2500base-x
111 - 5gbase-r
112 - rxaui
113 - 10gbase-r
115 port-id:
126 gop-port-id:
129 only for marvell,armada-7k-pp22, ID of the port from the
131 per-port registers in the second register area.
134 - reg
135 - interrupts
136 - phy-mode
137 - port-id
140 - compatible
141 - reg
142 - clocks
143 - clock-names
146 - if:
149 const: marvell,armada-7k-pp22
154 - description: Packet Processor registers
155 - description: Networking interfaces registers
156 - description: CM3 address space used for TX Flow Control
159 minItems: 5
161 clock-names:
162 minItems: 5
165 '^(ethernet-)?port@[0-2]$':
167 - gop-port-id
170 - marvell,system-controller
175 - description: Packet Processor registers
176 - description: LMS registers
177 - description: Register area per eth0
178 - description: Register area per eth1
183 clock-names:
187 '^(ethernet-)?port@[0-1]$':
192 gop-port-id: false
197 - |
199 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
200 #include <dt-bindings/interrupt-controller/arm-gic.h>
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "marvell,armada-375-pp2";
211 clock-names = "pp_clk", "gop_clk";
213 ethernet-port@0 {
216 port-id = <0>; /* For backward compatibility. */
218 phy-mode = "rgmii-id";
221 ethernet-port@1 {
224 port-id = <1>; /* For backward compatibility. */
226 phy-mode = "gmii";
230 - |
232 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
233 #include <dt-bindings/interrupt-controller/arm-gic.h>
236 #address-cells = <1>;
237 #size-cells = <0>;
238 compatible = "marvell,armada-7k-pp22";
241 <&cp0_clk 1 5>, <&cp0_clk 1 6>, <&cp0_clk 1 18>;
242 clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
243 marvell,system-controller = <&cp0_syscon0>;
245 ethernet-port@0 {
256 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
258 phy-mode = "10gbase-r";
261 port-id = <0>; /* For backward compatibility. */
262 gop-port-id = <0>;
265 ethernet-port@1 {
276 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
278 phy-mode = "rgmii-id";
280 port-id = <1>; /* For backward compatibility. */
281 gop-port-id = <2>;
284 ethernet-port@2 {
295 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
297 phy-mode = "2500base-x";
298 managed = "in-band-status";
302 port-id = <2>; /* For backward compatibility. */
303 gop-port-id = <3>;