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/linux/drivers/gpio/
H A Dgpio-104-idi-48.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
29 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
49 *mask = BIT(line); in idi_48_reg_mask_xlate()
87 #define IDI48_NGPIO 48
91 .mask = BIT((_id) / 8), \
96 IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
[all …]
/linux/include/uapi/linux/
H A Ddccp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 * struct dccp_hdr - generic part of DCCP packet header
11 * @dccph_sport - Relevant port on the endpoint that sent this packet
12 * @dccph_dport - Relevant port on the other endpoint
13 * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words
14 * @dccph_ccval - Used by the HC-Sender CCID
15 * @dccph_cscov - Parts of the packet that are covered by the Checksum field
16 * @dccph_checksum - Internet checksum, depends on dccph_cscov
17 * @dccph_x - 0 = 24 bit sequence number, 1 = 48
18 * @dccph_type - packet type, see DCCP_PKT_ prefixed macros
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H A Dhdreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
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/linux/lib/crc/arm/
H A Dcrc-t10dif-core.S2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
116 * Pairwise long polynomial multiplication of two 16-bit values
120 * by two 64-bit values
125 * significant. The resulting 80-bit vectors are XOR'ed together.
139 * 6 (w0*x6 ^ w1*x5) << 48 ^ | (y0*z6 ^ y1*z5) << 48 ^
148 * and after performing 8x8->16 bit long polynomial multiplication of
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/linux/Documentation/sound/cards/
H A Daudiophile-usb.rst2 Guide to using M-Audio Audiophile USB with ALSA and Jack
9 This document is a guide to using the M-Audio Audiophile USB (tm) device with
15 * v1.4 - Thibault Le Meur (2007-07-11)
17 - Added Low Endianness nature of 16bits-modes
19 - Modifying document structure
21 * v1.5 - Thibault Le Meur (2007-07-12)
22 - Added AC3/DTS passthru info
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
52 Please exit any audio application running before switching between bit depths
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/linux/lib/crc/arm64/
H A Dcrc-t10dif-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
5 // Copyright (C) 2019-2024 Google LLC
17 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
65 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
72 .arch armv8-a+crypto
96 * Pairwise long polynomial multiplication of two 16-bit values
100 * by two 64-bit values
119 * 6 (w0*x6 ^ w1*x5) << 48 ^ | (y0*z6 ^ y1*z5) << 48 ^
128 * and after performing 8x8->16 bit long polynomial multiplication of
130 * we obtain the following four vectors of 16-bit elements:
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/linux/arch/powerpc/kernel/vdso/
H A Dsigtramp32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 .Lsig_start = . - 4
43 .uleb128 9f - 1f; /* length */ \
56 .uleb128 9f - 1f; /* length */ \
65 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
72 .uleb128 9f - 1f; /* length */ \
97 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
102 .uleb128 9f - 1f; /* length */ \
105 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
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H A Dsigtramp64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 .quad 0,-21*8
48 .uleb128 9f - 1f; /* length */ \
61 .uleb128 9f - 1f; /* length */ \
70 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
77 .uleb128 9f - 1f; /* length */ \
103 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
108 .uleb128 9f - 1f; /* length */ \
111 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
114 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
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/linux/lib/crc/x86/
H A Dcrc-pclmul-consts.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 …* ./scripts/gen-crc-consts.py x86_pclmul crc16_msb_0x8bb7,crc32_lsb_0xedb88320,crc32_lsb_0x82f63b7…
11 * CRC folding constants generated for most-significant-bit-first CRC-16 using
21 u8 shuf_table[48];
26 0xdccf000000000000, /* LO64_TERMS: (x^2000 mod G) * x^48 */
27 0x4b0b000000000000, /* HI64_TERMS: (x^2064 mod G) * x^48 */
30 0x9d9d000000000000, /* LO64_TERMS: (x^976 mod G) * x^48 */
31 0x7cf5000000000000, /* HI64_TERMS: (x^1040 mod G) * x^48 */
34 0x044c000000000000, /* LO64_TERMS: (x^464 mod G) * x^48 */
35 0xe658000000000000, /* HI64_TERMS: (x^528 mod G) * x^48 */
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/linux/drivers/net/ethernet/microsoft/mana/
H A Dshm_channel.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
17 #define SHMEM_VF_RESET_STATE ((u32)-1)
38 * direction: 0 for request, VF->PF; 1 for response, PF->VF.
67 #define SMC_LAST_DWORD (SMC_APERTURE_DWORDS - 1)
75 /* Poll the hardware for the ownership bit. This should be pretty fast, in mana_smc_poll_register()
87 if (!(last_dword & BIT(31))) in mana_smc_poll_register()
93 return -ETIMEDOUT; in mana_smc_poll_register()
99 void __iomem *base = sc->base; in mana_smc_read_response()
116 dev_err(sc->dev, "Wrong SMC response 0x%x, type=%d, ver=%d\n", in mana_smc_read_response()
118 return -EPROTO; in mana_smc_read_response()
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/linux/sound/pci/emu10k1/
H A Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
73 * [19:16] Playback mixer output enable. 1 bit per channel.
74 * [23:20] Capture mixer output enable. 1 bit per channel.
75 * [26:24] FX engine channel capture 0 = 0x60-0x67.
76 * 1 = 0x68-0x6f.
77 * 2 = 0x70-0x77.
78 * 3 = 0x78-0x7f.
[all …]
/linux/include/sound/
H A Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ----
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/linux/arch/mips/loongson64/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
10 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
11 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
19 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
20 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
/linux/arch/alpha/kernel/
H A Dsys_wildfire.c1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_lmtt_ml.c1 // SPDX-License-Identifier: MIT
15 * DOC: Multi-Level LMTT Structure
17 * LMHAW (Local Memory Host Address Width) is 48 bit (256TB)
19 * LMGAW (Local Memory Guest Address Width) is 48 bit (256TB)
25 * +-----------+ +-----------+
27 * | | +-----------+ | |
29 * | | | | GDPA --> | PTE | => LMEM PF offset
33 * | | offset -> | PTE | ----------> +-----------+
34 * | | GAW-1:35 +===========+ / \.
36 * VFID --> | PDE | ---------> +-----------+ / \.
[all …]
/linux/include/soc/fsl/
H A Dbman.h1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
34 /* wrapper for 48-bit buffers */
38 __be16 bpid; /* hi 8-bits reserved */
39 __be16 hi; /* High 16-bits of 48-bit address */
40 __be32 lo; /* Low 32-bits of 48-bit address */
46 * Restore the 48 bit address previously stored in BMan
51 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buf_addr()
56 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buffer_get64()
61 buf->hi = cpu_to_be16(upper_32_bits(addr)); in bm_buffer_set64()
62 buf->lo = cpu_to_be32(lower_32_bits(addr)); in bm_buffer_set64()
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/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Applied Micro X-Gene SoC Ethernet Driver
22 u32 end = start + len - 1; in xgene_set_bits()
41 #define OVERWRITE BIT(31)
42 #define IS_BUFFER_POOL BIT(20)
43 #define PREFETCH_BUF_EN BIT(21)
61 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
62 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
92 #define ACCEPTLERR BIT(19)
93 #define QCOHERENT BIT(4)
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/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0
46 #define OTX_CPT_VF_INTR_MBOX_MASK BIT(0)
47 #define OTX_CPT_VF_INTR_DOVF_MASK BIT(1)
48 #define OTX_CPT_VF_INTR_IRDE_MASK BIT(2)
49 #define OTX_CPT_VF_INTR_NWRP_MASK BIT(3)
50 #define OTX_CPT_VF_INTR_SERR_MASK BIT(4)
154 * CPT OcteonTX VF MSI-X Vector Enumeration
155 * Enumerates the MSI-X interrupt vectors.
167 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
179 * Address must be 16-byte aligned.
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/linux/arch/powerpc/lib/
H A Dchecksum_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains assembly-language implementations
4 * of IP-style 1's complement checksum routines.
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
19 * and adds in "sum" (32-bit).
35 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
62 stdu r1,-STACKFRAMESIZE(r1)
86 ld r15,48(r3)
113 ld r15,48(r3)
176 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
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/linux/arch/parisc/kernel/
H A Dsignal32.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2001 Matthew Wilcox <willy at parisc-linux.org>
4 * Copyright (C) 2003 Carlos O'Donell <carlos at parisc-linux.org>
11 /* 32-bit ucontext as seen from an 64-bit kernel */
16 /* FIXME: Pad out to get uc_mcontext to start at an 8-byte aligned boundary */
24 /* In a deft move of uber-hackery, we decide to carry the top half of all
25 * 64-bit registers in a non-portable, non-ABI, hidden structure.
31 /* Upper half of all the 64-bit registers that were truncated
32 on a copy to a 32-bit userspace */
48 * The 32-bit ABI wants at least 48 bytes for a function call frame:
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/linux/drivers/net/ethernet/sfc/
H A Dmae_counter_format.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 /* Format of counter packets (version 2) from the ef100 Match-Action Engine */
17 /*------------------------------------------------------------*/
19 * ER_RX_SL_PACKETISER_HEADER_WORD(160bit):
41 #define ERF_SC_PACKETISER_HEADER_COUNT_LBN 48
51 /*------------------------------------------------------------*/
53 * ER_RX_SL_PACKETISER_PAYLOAD_WORD(128bit):
66 #define ERF_SC_PACKETISER_PAYLOAD_PACKET_COUNT_WIDTH 48
70 #define ERF_SC_PACKETISER_PAYLOAD_BYTE_COUNT_WIDTH 48
/linux/drivers/crypto/cavium/cpt/
H A Dcpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
42 * Address must be 16-byte aligned.
44 * sign-extended bit <48> for forward compatibility.
46 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
48 * For the SSO to not discard the add-work request, FPA_PF_MAP() must map
56 * work-queue entry that CPT submits work to SSO after all context,
60 * use a sign-extended bit <48> for forward compatibility.
76 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
80 #else /* Word 0 - Little Endian */
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/linux/drivers/clk/pxa/
H A Dclk-pxa3xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
14 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
44 #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
46 #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
47 #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */
58 * Clock Enable Bit
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/linux/lib/842/
H A D842_compress.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 * use the non-standard "short data" template so the decompressor can correctly
54 { I2, I2, D4, N0, 0x0f }, /* 48 */
55 { I2, D2, I2, D2, 0x0c }, /* 48 */
56 { I2, D4, I2, N0, 0x0b }, /* 48 */
57 { D2, I2, I2, D2, 0x07 }, /* 48 */
94 u8 bit; global() member
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/linux/Documentation/arch/m68k/
H A Dbuddha-driver.rst8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
32 $48, while it doesn't matter how often you're writing to $4a
33 as long as $48 is not touched. After $48 has been written,
35 address just written. Make sure $4a is written before $48,
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