Lines Matching +full:48 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
28 #define MAXPAGES0 4096 /* 32 bit mode */
29 #define MAXPAGES1 8192 /* 31 bit mode */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
34 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
41 // This is used to define hardware bit-fields (sub-registers) by combining
42 // the bit shift and count with the actual register address. The passed
44 // The non-concatenating (_NC) variant should be used directly only for
45 // sub-registers that do not follow the <register>_<field> naming pattern.
55 // Macros for manipulating values of bit-fields declared using the above macros.
59 // single sub-register at a time.
62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
79 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
81 /* accessed. For non per-channel registers the */
91 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
117 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
129 /* the bit in H/CLIPL or H/CLIPH corresponding */
134 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
139 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
143 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
144 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
145 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
146 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
148 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
161 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
162 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
168 /* NOTE: This bit must always be enabled */
180 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
181 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
215 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
216 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
219 /* they are not rate-locked to the external */
223 /* the SPDIF V-bit indicates invalid audio */
237 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
238 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
249 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
255 /* they are not rate-locked to the external */
267 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
271 // On Audigy, the MPU port moved to the 0x70-0x74 ptr registers
290 // card-specific info can be found in the emu_chip_details table.
291 // On E-MU cards the port is used as the interface to the FPGA.
300 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
317 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
319 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
320 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
346 /* 0x00000000 2-channel output. */
347 /* 0x00000200 8-channel output. */
350 /* bit 0: Enable P16V audio.
351 * bit 1: Lock P16V record memory cache.
352 * bit 2: Lock P16V playback memory cache.
353 * bit 3: Dummy record insert zero samples.
354 * bit 8: Record 8-channel in phase.
355 * bit 9: Playback 8-channel in phase.
356 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
357 * bit 13: Playback mixer enable.
358 * bit 14: Route SRC48 mixer output to fx engine.
359 * bit 15: Enable IEEE 1394 chip.
383 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
388 // "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers
389 // "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view
392 // - The engine has 64 playback channels, also called voices. The channels
394 // - PCM samples are fetched into the cache; see description of CD0 below.
395 // - Samples are consumed at the rate CPF_CURRENTPITCH.
396 // - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8
397 // - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated
400 // - The value is multiplied by CVCF_CURRENTVOL.
401 // - The value goes through a filter with cutoff CVCF_CURRENTFILTER;
403 // - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2)
405 // multiplied by a per-send amount (*_FXSENDAMOUNT_*).
406 // The scaling of the send amounts is exponential-ish.
407 // - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*.
408 // - The pitch, volume, and filter cutoff can be modulated by two envelope
410 // - To avoid abrupt changes to the parameters (which may cause audible
417 // The somewhat non-obviously still meaningful ones are:
426 /* Can be set only while matching bit in SOLEx is 1 */
471 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
472 /* 8-bit samples are unsigned, 16-bit ones signed */
479 /* Auto-set from CPF_STEREO_MASK */
481 /* Auto-set from CCCA_8BITSELECT */
504 #define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */
507 #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
513 /* 0x8000-n == 666*n usec delay */
517 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
532 /* 0x8000-n == 666*n usec delay */
536 /* 0x8000-n == 666*n usec delay */
540 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
552 /* 0x8000-n == 666*n usec delay */
567 /* Signed 2's complement, +/- one octave peak extremes */
569 /* Signed 2's complement, +/- six octaves peak extremes */
574 /* Signed 2's complement, +/- one octave extremes */
576 /* Signed 2's complement, +/- three octave extremes */
580 /* Signed 2's complement, with +/- 12dB extremes */
586 /* Signed 2's complement, +/- one octave extremes */
591 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
600 // The cache holds 64 frames, so the upper half is not used in 8-bit mode.
607 // The cache is filled from (CA - CIS) into (CRA - CIS).
609 // CIS below 8 (16-bit stereo), 16 (16-bit mono, 8-bit stereo), or
610 // 32 (8-bit mono). The actual transfers are pretty unpredictable,
619 // filled from (CLA - LIS), and CLF is subsequently reset.
638 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
651 /* When set, each bit enables the writing of the */
653 /* 0x20-0x3f) to host memory. This mode of recording */
654 /* is 16bit, 48KHz only. All 32 channels can be enabled */
671 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
674 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
677 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
679 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
728 // NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1)
729 #define CDCS 0x50 /* CD-ROM digital channel status register */
743 // NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
756 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
764 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
765 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
766 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
770 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
772 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
776 /* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */
784 // Subsequent changes to the address registers don't resume; clearing the bit here or in CPF does.
792 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
793 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
803 // NOTE: 0x60,61,62: 64-bit
804 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
818 /* Note that these values can vary +/- by a small amount */
838 /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */
865 /* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */
866 /* Each bit selects a channel for recording */
867 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
868 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
895 #define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 19…
905 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
913 // In A_FXRT1 & A_FXRT2, the 0x80 bit of each byte completely disables the
949 /* E-MU Digital Audio System overview */
952 // - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2);
954 // - All physical PCM I/O is routed through an additional FPGA; the regular
956 // - The FPGA has a signal routing matrix, to connect each destination (output
958 // - The FPGA is controlled via Audigy's GPIO port, while sample data is
959 // transmitted via proprietary EMU32 serial links. On first-generation
960 // E-MU 1010 cards, Audigy's I2S inputs are also used for sample data.
961 // - The Audio/Micro Dock is attached to Hana via EDI, a "network" link.
962 // - The Audigy chip operates in slave mode; the clock is supplied by the FPGA.
963 // Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples),
965 // - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz
966 // sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels
968 // - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total
970 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
973 // - The code names are mentioned below and in the emu_chip_details table.
1042 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1044 #define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */
1045 #define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */
1047 #define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */
1048 #define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */
1050 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
1056 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
1058 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1064 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
1072 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1078 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1088 #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
1095 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1102 /* 0x14 - 0x1f Unused R/W registers */
1117 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1118 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1120 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1121 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1124 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1125 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1127 // The actual code disagrees about the bit width of the registers -
1130 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1131 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1133 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1134 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1136 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1137 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1139 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1140 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1142 /* 0x30 - 0x3f Unused Read only registers */
1144 // The meaning of this is not clear; kX-project just calls it "lock" in some info-only code.
1152 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1153 * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock
1170 * 0x04, 0x00-0x07: Hana ADAT
1182 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1183 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1192 * 0x18-0x1f: Dock ADAT 0-7
1197 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1198 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1199 * 0x06-0x07: Not used
1203 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina
1209 * 0x04-0x07: Not used
1212 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1213 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1218 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1219 * 0x05-0x07: Not used
1222 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1223 * physical outputs of Hana, or outputs going to Alice2/Tina for capture -
1225 * a channel depends on the mixer control setting for each destination - see
1245 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1249 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1253 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1257 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1261 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1265 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1267 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1271 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1273 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1277 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1279 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1283 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1285 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1289 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1293 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1297 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1312 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1314 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1318 #define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1319 #define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1325 * 0x00, 0x00-0x1f: Silence
1326 * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock
1337 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1338 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1339 * 0x04, 0x00-0x07: Hana ADAT
1342 * 0x06-0x07: Not used
1348 * 0x00, 0x00-0x1f: Silence
1349 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1358 * 0x18-0x1f: Dock ADAT 0-7
1361 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1362 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1363 * 0x04, 0x00-0x07: Hana3 ADAT
1366 * 0x06-0x07: Not used
1370 * 0x00, 0x00-0x1f: Silence
1374 * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output
1375 * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output
1379 * 0x06-0x07: Not used
1382 * 0x00, 0x00-0x1f: Silence
1383 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1386 * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output
1387 * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output
1388 * 0x04-0x07: Not used
1391 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1392 * destinations using a mixer control for each destination - see emumixer.c.
1393 * Sources are either physical inputs of Hana, or inputs from Alice2/Tina -
1397 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1401 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1405 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1409 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1413 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1417 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1421 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1425 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1429 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1433 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1441 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1445 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1452 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */
1454 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */
1461 /* ------------------- CONSTANTS -------------------- */
1470 /* ------------------- STRUCTURES -------------------- */
1557 …efine snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (P…
1586 unsigned int channels; /* 16-bit channels count */
1641 // Chip-o-logy:
1642 // - All SB Live! cards use EMU10K1 chips
1643 // - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver
1644 // - Original Audigy uses CA0100 "Alice"
1645 // - Audigy 2 uses CA0102/CA10200 "Alice2"
1646 // - Has an interface for CA0151 (P16V) "Alice3"
1647 // - Audigy 2 Value uses CA0108/CA10300 "Tina"
1648 // - Approximately a CA0102 with an on-chip CA0151 (P17V)
1649 // - Audigy 2 ZS NB uses CA0109 "Tina2"
1650 // - Cardbus version of CA0108
1657 unsigned int emu10k1_chip:1; /* Original SB Live. Not SB Live 24bit. */
1668 unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1678 const char *id; /* for backward compatibility - can be NULL if not needed */
1687 unsigned int adc_pads; /* bit mask */
1688 unsigned int dac_pads; /* bit mask */
1752 spinlock_t reg_lock; // high-level driver lock
1753 spinlock_t emu_lock; // low-level i/o lock
1845 static inline void snd_emu1010_fpga_lock(struct snd_emu10k1 *emu) { mutex_lock(&emu->emu1010.lock);… in snd_emu1010_fpga_lock()
1846 static inline void snd_emu1010_fpga_unlock(struct snd_emu10k1 *emu) { mutex_unlock(&emu->emu1010.lo… in snd_emu1010_fpga_unlock()
1872 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >>… in snd_emu10k1_wc()