Lines Matching +full:48 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
123 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
214 IRDMA_OP_CQ_MODIFY = 48,
360 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
409 #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)
428 #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
432 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
477 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
519 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
541 #define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)
556 #define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)
578 #define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48)
596 #define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)
628 /* Manage Push Page - MPP */
638 /* Upload Context - UCTX */
641 #define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)
672 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
739 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
747 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
756 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
788 #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
820 #define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)
835 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
863 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
872 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
890 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
902 #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)
903 #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)
904 #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)
922 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
927 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
932 (_ceq)->ceqe_base[_pos].buf \
944 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
949 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
970 (_retcode) = -ENOMEM; \
981 (_retcode) = -ENOMEM; \
992 (_retcode) = -ENOMEM; \
999 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1003 (_retcode) = -ENOMEM; \
1023 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1028 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1033 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1038 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1043 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1047 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1056 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1061 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1066 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1089 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1090 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1091 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1092 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1093 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1094 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1095 IRDMA_SHADOWAREA_M = (128 - 1),
1096 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1097 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1116 * set_64bit_val - set 64 bit value to hw wqe
1127 * set_32bit_val - set 32 bit value to hw wqe
1138 * get_64bit_val - read 64 bit value from wqe
1149 * get_32bit_val - read 32 bit value from wqe
1152 * @val: return 32 bit value