1*fd1feadeSChristophe Leroy/* SPDX-License-Identifier: GPL-2.0-or-later */ 2*fd1feadeSChristophe Leroy/* 3*fd1feadeSChristophe Leroy * Signal trampolines for 32 bits processes in a ppc64 kernel for 4*fd1feadeSChristophe Leroy * use in the vDSO 5*fd1feadeSChristophe Leroy * 6*fd1feadeSChristophe Leroy * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp. 7*fd1feadeSChristophe Leroy * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp. 8*fd1feadeSChristophe Leroy */ 9*fd1feadeSChristophe Leroy#include <asm/processor.h> 10*fd1feadeSChristophe Leroy#include <asm/ppc_asm.h> 11*fd1feadeSChristophe Leroy#include <asm/unistd.h> 12*fd1feadeSChristophe Leroy#include <asm/vdso.h> 13*fd1feadeSChristophe Leroy 14*fd1feadeSChristophe Leroy .text 15*fd1feadeSChristophe Leroy 16*fd1feadeSChristophe Leroy/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from 17*fd1feadeSChristophe Leroy the return address to get an address in the middle of the presumed 18*fd1feadeSChristophe Leroy call instruction. Since we don't have a call here, we artificially 19*fd1feadeSChristophe Leroy extend the range covered by the unwind info by adding a nop before 20*fd1feadeSChristophe Leroy the real start. */ 21*fd1feadeSChristophe Leroy nop 22*fd1feadeSChristophe LeroyV_FUNCTION_BEGIN(__kernel_sigtramp32) 23*fd1feadeSChristophe Leroy.Lsig_start = . - 4 24*fd1feadeSChristophe Leroy li r0,__NR_sigreturn 25*fd1feadeSChristophe Leroy sc 26*fd1feadeSChristophe Leroy.Lsig_end: 27*fd1feadeSChristophe LeroyV_FUNCTION_END(__kernel_sigtramp32) 28*fd1feadeSChristophe Leroy 29*fd1feadeSChristophe Leroy.Lsigrt_start: 30*fd1feadeSChristophe Leroy nop 31*fd1feadeSChristophe LeroyV_FUNCTION_BEGIN(__kernel_sigtramp_rt32) 32*fd1feadeSChristophe Leroy li r0,__NR_rt_sigreturn 33*fd1feadeSChristophe Leroy sc 34*fd1feadeSChristophe Leroy.Lsigrt_end: 35*fd1feadeSChristophe LeroyV_FUNCTION_END(__kernel_sigtramp_rt32) 36*fd1feadeSChristophe Leroy 37*fd1feadeSChristophe Leroy .section .eh_frame,"a",@progbits 38*fd1feadeSChristophe Leroy 39*fd1feadeSChristophe Leroy/* Register r1 can be found at offset 4 of a pt_regs structure. 40*fd1feadeSChristophe Leroy A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */ 41*fd1feadeSChristophe Leroy#define cfa_save \ 42*fd1feadeSChristophe Leroy .byte 0x0f; /* DW_CFA_def_cfa_expression */ \ 43*fd1feadeSChristophe Leroy .uleb128 9f - 1f; /* length */ \ 44*fd1feadeSChristophe Leroy1: \ 45*fd1feadeSChristophe Leroy .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ 46*fd1feadeSChristophe Leroy .byte 0x06; /* DW_OP_deref */ \ 47*fd1feadeSChristophe Leroy .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \ 48*fd1feadeSChristophe Leroy .byte 0x06; /* DW_OP_deref */ \ 49*fd1feadeSChristophe Leroy9: 50*fd1feadeSChristophe Leroy 51*fd1feadeSChristophe Leroy/* Register REGNO can be found at offset OFS of a pt_regs structure. 52*fd1feadeSChristophe Leroy A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */ 53*fd1feadeSChristophe Leroy#define rsave(regno, ofs) \ 54*fd1feadeSChristophe Leroy .byte 0x10; /* DW_CFA_expression */ \ 55*fd1feadeSChristophe Leroy .uleb128 regno; /* regno */ \ 56*fd1feadeSChristophe Leroy .uleb128 9f - 1f; /* length */ \ 57*fd1feadeSChristophe Leroy1: \ 58*fd1feadeSChristophe Leroy .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ 59*fd1feadeSChristophe Leroy .byte 0x06; /* DW_OP_deref */ \ 60*fd1feadeSChristophe Leroy .ifne ofs; \ 61*fd1feadeSChristophe Leroy .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \ 62*fd1feadeSChristophe Leroy .endif; \ 63*fd1feadeSChristophe Leroy9: 64*fd1feadeSChristophe Leroy 65*fd1feadeSChristophe Leroy/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 66*fd1feadeSChristophe Leroy of the VMX reg struct. The VMX reg struct is at offset VREGS of 67*fd1feadeSChristophe Leroy the pt_regs struct. This macro is for REGNO == 0, and contains 68*fd1feadeSChristophe Leroy 'subroutines' that the other macros jump to. */ 69*fd1feadeSChristophe Leroy#define vsave_msr0(regno) \ 70*fd1feadeSChristophe Leroy .byte 0x10; /* DW_CFA_expression */ \ 71*fd1feadeSChristophe Leroy .uleb128 regno + 77; /* regno */ \ 72*fd1feadeSChristophe Leroy .uleb128 9f - 1f; /* length */ \ 73*fd1feadeSChristophe Leroy1: \ 74*fd1feadeSChristophe Leroy .byte 0x30 + regno; /* DW_OP_lit0 */ \ 75*fd1feadeSChristophe Leroy2: \ 76*fd1feadeSChristophe Leroy .byte 0x40; /* DW_OP_lit16 */ \ 77*fd1feadeSChristophe Leroy .byte 0x1e; /* DW_OP_mul */ \ 78*fd1feadeSChristophe Leroy3: \ 79*fd1feadeSChristophe Leroy .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ 80*fd1feadeSChristophe Leroy .byte 0x06; /* DW_OP_deref */ \ 81*fd1feadeSChristophe Leroy .byte 0x12; /* DW_OP_dup */ \ 82*fd1feadeSChristophe Leroy .byte 0x23; /* DW_OP_plus_uconst */ \ 83*fd1feadeSChristophe Leroy .uleb128 33*RSIZE; /* msr offset */ \ 84*fd1feadeSChristophe Leroy .byte 0x06; /* DW_OP_deref */ \ 85*fd1feadeSChristophe Leroy .byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \ 86*fd1feadeSChristophe Leroy .byte 0x1a; /* DW_OP_and */ \ 87*fd1feadeSChristophe Leroy .byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \ 88*fd1feadeSChristophe Leroy .byte 0x30; /* DW_OP_lit0 */ \ 89*fd1feadeSChristophe Leroy .byte 0x29; /* DW_OP_eq */ \ 90*fd1feadeSChristophe Leroy .byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \ 91*fd1feadeSChristophe Leroy .byte 0x13; /* DW_OP_drop, pop the 0 */ \ 92*fd1feadeSChristophe Leroy .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \ 93*fd1feadeSChristophe Leroy .byte 0x22; /* DW_OP_plus */ \ 94*fd1feadeSChristophe Leroy .byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \ 95*fd1feadeSChristophe Leroy9: 96*fd1feadeSChristophe Leroy 97*fd1feadeSChristophe Leroy/* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 98*fd1feadeSChristophe Leroy of the VMX reg struct. REGNO is 1 thru 31. */ 99*fd1feadeSChristophe Leroy#define vsave_msr1(regno) \ 100*fd1feadeSChristophe Leroy .byte 0x10; /* DW_CFA_expression */ \ 101*fd1feadeSChristophe Leroy .uleb128 regno + 77; /* regno */ \ 102*fd1feadeSChristophe Leroy .uleb128 9f - 1f; /* length */ \ 103*fd1feadeSChristophe Leroy1: \ 104*fd1feadeSChristophe Leroy .byte 0x30 + regno; /* DW_OP_lit n */ \ 105*fd1feadeSChristophe Leroy .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \ 106*fd1feadeSChristophe Leroy9: 107*fd1feadeSChristophe Leroy 108*fd1feadeSChristophe Leroy/* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of 109*fd1feadeSChristophe Leroy the VMX save block. */ 110*fd1feadeSChristophe Leroy#define vsave_msr2(regno, ofs) \ 111*fd1feadeSChristophe Leroy .byte 0x10; /* DW_CFA_expression */ \ 112*fd1feadeSChristophe Leroy .uleb128 regno + 77; /* regno */ \ 113*fd1feadeSChristophe Leroy .uleb128 9f - 1f; /* length */ \ 114*fd1feadeSChristophe Leroy1: \ 115*fd1feadeSChristophe Leroy .byte 0x0a; .short ofs; /* DW_OP_const2u */ \ 116*fd1feadeSChristophe Leroy .byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \ 117*fd1feadeSChristophe Leroy9: 118*fd1feadeSChristophe Leroy 119*fd1feadeSChristophe Leroy/* VMX register REGNO is at offset OFS of the VMX save area. */ 120*fd1feadeSChristophe Leroy#define vsave(regno, ofs) \ 121*fd1feadeSChristophe Leroy .byte 0x10; /* DW_CFA_expression */ \ 122*fd1feadeSChristophe Leroy .uleb128 regno + 77; /* regno */ \ 123*fd1feadeSChristophe Leroy .uleb128 9f - 1f; /* length */ \ 124*fd1feadeSChristophe Leroy1: \ 125*fd1feadeSChristophe Leroy .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ 126*fd1feadeSChristophe Leroy .byte 0x06; /* DW_OP_deref */ \ 127*fd1feadeSChristophe Leroy .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \ 128*fd1feadeSChristophe Leroy .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \ 129*fd1feadeSChristophe Leroy9: 130*fd1feadeSChristophe Leroy 131*fd1feadeSChristophe Leroy/* This is where the pt_regs pointer can be found on the stack. */ 132*fd1feadeSChristophe Leroy#define PTREGS 64+28 133*fd1feadeSChristophe Leroy 134*fd1feadeSChristophe Leroy/* Size of regs. */ 135*fd1feadeSChristophe Leroy#define RSIZE 4 136*fd1feadeSChristophe Leroy 137*fd1feadeSChristophe Leroy/* This is the offset of the VMX regs. */ 138*fd1feadeSChristophe Leroy#define VREGS 48*RSIZE+34*8 139*fd1feadeSChristophe Leroy 140*fd1feadeSChristophe Leroy/* Describe where general purpose regs are saved. */ 141*fd1feadeSChristophe Leroy#define EH_FRAME_GEN \ 142*fd1feadeSChristophe Leroy cfa_save; \ 143*fd1feadeSChristophe Leroy rsave ( 0, 0*RSIZE); \ 144*fd1feadeSChristophe Leroy rsave ( 2, 2*RSIZE); \ 145*fd1feadeSChristophe Leroy rsave ( 3, 3*RSIZE); \ 146*fd1feadeSChristophe Leroy rsave ( 4, 4*RSIZE); \ 147*fd1feadeSChristophe Leroy rsave ( 5, 5*RSIZE); \ 148*fd1feadeSChristophe Leroy rsave ( 6, 6*RSIZE); \ 149*fd1feadeSChristophe Leroy rsave ( 7, 7*RSIZE); \ 150*fd1feadeSChristophe Leroy rsave ( 8, 8*RSIZE); \ 151*fd1feadeSChristophe Leroy rsave ( 9, 9*RSIZE); \ 152*fd1feadeSChristophe Leroy rsave (10, 10*RSIZE); \ 153*fd1feadeSChristophe Leroy rsave (11, 11*RSIZE); \ 154*fd1feadeSChristophe Leroy rsave (12, 12*RSIZE); \ 155*fd1feadeSChristophe Leroy rsave (13, 13*RSIZE); \ 156*fd1feadeSChristophe Leroy rsave (14, 14*RSIZE); \ 157*fd1feadeSChristophe Leroy rsave (15, 15*RSIZE); \ 158*fd1feadeSChristophe Leroy rsave (16, 16*RSIZE); \ 159*fd1feadeSChristophe Leroy rsave (17, 17*RSIZE); \ 160*fd1feadeSChristophe Leroy rsave (18, 18*RSIZE); \ 161*fd1feadeSChristophe Leroy rsave (19, 19*RSIZE); \ 162*fd1feadeSChristophe Leroy rsave (20, 20*RSIZE); \ 163*fd1feadeSChristophe Leroy rsave (21, 21*RSIZE); \ 164*fd1feadeSChristophe Leroy rsave (22, 22*RSIZE); \ 165*fd1feadeSChristophe Leroy rsave (23, 23*RSIZE); \ 166*fd1feadeSChristophe Leroy rsave (24, 24*RSIZE); \ 167*fd1feadeSChristophe Leroy rsave (25, 25*RSIZE); \ 168*fd1feadeSChristophe Leroy rsave (26, 26*RSIZE); \ 169*fd1feadeSChristophe Leroy rsave (27, 27*RSIZE); \ 170*fd1feadeSChristophe Leroy rsave (28, 28*RSIZE); \ 171*fd1feadeSChristophe Leroy rsave (29, 29*RSIZE); \ 172*fd1feadeSChristophe Leroy rsave (30, 30*RSIZE); \ 173*fd1feadeSChristophe Leroy rsave (31, 31*RSIZE); \ 174*fd1feadeSChristophe Leroy rsave (67, 32*RSIZE); /* ap, used as temp for nip */ \ 175*fd1feadeSChristophe Leroy rsave (65, 36*RSIZE); /* lr */ \ 176*fd1feadeSChristophe Leroy rsave (70, 38*RSIZE) /* cr */ 177*fd1feadeSChristophe Leroy 178*fd1feadeSChristophe Leroy/* Describe where the FP regs are saved. */ 179*fd1feadeSChristophe Leroy#define EH_FRAME_FP \ 180*fd1feadeSChristophe Leroy rsave (32, 48*RSIZE + 0*8); \ 181*fd1feadeSChristophe Leroy rsave (33, 48*RSIZE + 1*8); \ 182*fd1feadeSChristophe Leroy rsave (34, 48*RSIZE + 2*8); \ 183*fd1feadeSChristophe Leroy rsave (35, 48*RSIZE + 3*8); \ 184*fd1feadeSChristophe Leroy rsave (36, 48*RSIZE + 4*8); \ 185*fd1feadeSChristophe Leroy rsave (37, 48*RSIZE + 5*8); \ 186*fd1feadeSChristophe Leroy rsave (38, 48*RSIZE + 6*8); \ 187*fd1feadeSChristophe Leroy rsave (39, 48*RSIZE + 7*8); \ 188*fd1feadeSChristophe Leroy rsave (40, 48*RSIZE + 8*8); \ 189*fd1feadeSChristophe Leroy rsave (41, 48*RSIZE + 9*8); \ 190*fd1feadeSChristophe Leroy rsave (42, 48*RSIZE + 10*8); \ 191*fd1feadeSChristophe Leroy rsave (43, 48*RSIZE + 11*8); \ 192*fd1feadeSChristophe Leroy rsave (44, 48*RSIZE + 12*8); \ 193*fd1feadeSChristophe Leroy rsave (45, 48*RSIZE + 13*8); \ 194*fd1feadeSChristophe Leroy rsave (46, 48*RSIZE + 14*8); \ 195*fd1feadeSChristophe Leroy rsave (47, 48*RSIZE + 15*8); \ 196*fd1feadeSChristophe Leroy rsave (48, 48*RSIZE + 16*8); \ 197*fd1feadeSChristophe Leroy rsave (49, 48*RSIZE + 17*8); \ 198*fd1feadeSChristophe Leroy rsave (50, 48*RSIZE + 18*8); \ 199*fd1feadeSChristophe Leroy rsave (51, 48*RSIZE + 19*8); \ 200*fd1feadeSChristophe Leroy rsave (52, 48*RSIZE + 20*8); \ 201*fd1feadeSChristophe Leroy rsave (53, 48*RSIZE + 21*8); \ 202*fd1feadeSChristophe Leroy rsave (54, 48*RSIZE + 22*8); \ 203*fd1feadeSChristophe Leroy rsave (55, 48*RSIZE + 23*8); \ 204*fd1feadeSChristophe Leroy rsave (56, 48*RSIZE + 24*8); \ 205*fd1feadeSChristophe Leroy rsave (57, 48*RSIZE + 25*8); \ 206*fd1feadeSChristophe Leroy rsave (58, 48*RSIZE + 26*8); \ 207*fd1feadeSChristophe Leroy rsave (59, 48*RSIZE + 27*8); \ 208*fd1feadeSChristophe Leroy rsave (60, 48*RSIZE + 28*8); \ 209*fd1feadeSChristophe Leroy rsave (61, 48*RSIZE + 29*8); \ 210*fd1feadeSChristophe Leroy rsave (62, 48*RSIZE + 30*8); \ 211*fd1feadeSChristophe Leroy rsave (63, 48*RSIZE + 31*8) 212*fd1feadeSChristophe Leroy 213*fd1feadeSChristophe Leroy/* Describe where the VMX regs are saved. */ 214*fd1feadeSChristophe Leroy#ifdef CONFIG_ALTIVEC 215*fd1feadeSChristophe Leroy#define EH_FRAME_VMX \ 216*fd1feadeSChristophe Leroy vsave_msr0 ( 0); \ 217*fd1feadeSChristophe Leroy vsave_msr1 ( 1); \ 218*fd1feadeSChristophe Leroy vsave_msr1 ( 2); \ 219*fd1feadeSChristophe Leroy vsave_msr1 ( 3); \ 220*fd1feadeSChristophe Leroy vsave_msr1 ( 4); \ 221*fd1feadeSChristophe Leroy vsave_msr1 ( 5); \ 222*fd1feadeSChristophe Leroy vsave_msr1 ( 6); \ 223*fd1feadeSChristophe Leroy vsave_msr1 ( 7); \ 224*fd1feadeSChristophe Leroy vsave_msr1 ( 8); \ 225*fd1feadeSChristophe Leroy vsave_msr1 ( 9); \ 226*fd1feadeSChristophe Leroy vsave_msr1 (10); \ 227*fd1feadeSChristophe Leroy vsave_msr1 (11); \ 228*fd1feadeSChristophe Leroy vsave_msr1 (12); \ 229*fd1feadeSChristophe Leroy vsave_msr1 (13); \ 230*fd1feadeSChristophe Leroy vsave_msr1 (14); \ 231*fd1feadeSChristophe Leroy vsave_msr1 (15); \ 232*fd1feadeSChristophe Leroy vsave_msr1 (16); \ 233*fd1feadeSChristophe Leroy vsave_msr1 (17); \ 234*fd1feadeSChristophe Leroy vsave_msr1 (18); \ 235*fd1feadeSChristophe Leroy vsave_msr1 (19); \ 236*fd1feadeSChristophe Leroy vsave_msr1 (20); \ 237*fd1feadeSChristophe Leroy vsave_msr1 (21); \ 238*fd1feadeSChristophe Leroy vsave_msr1 (22); \ 239*fd1feadeSChristophe Leroy vsave_msr1 (23); \ 240*fd1feadeSChristophe Leroy vsave_msr1 (24); \ 241*fd1feadeSChristophe Leroy vsave_msr1 (25); \ 242*fd1feadeSChristophe Leroy vsave_msr1 (26); \ 243*fd1feadeSChristophe Leroy vsave_msr1 (27); \ 244*fd1feadeSChristophe Leroy vsave_msr1 (28); \ 245*fd1feadeSChristophe Leroy vsave_msr1 (29); \ 246*fd1feadeSChristophe Leroy vsave_msr1 (30); \ 247*fd1feadeSChristophe Leroy vsave_msr1 (31); \ 248*fd1feadeSChristophe Leroy vsave_msr2 (33, 32*16+12); \ 249*fd1feadeSChristophe Leroy vsave (32, 32*16) 250*fd1feadeSChristophe Leroy#else 251*fd1feadeSChristophe Leroy#define EH_FRAME_VMX 252*fd1feadeSChristophe Leroy#endif 253*fd1feadeSChristophe Leroy 254*fd1feadeSChristophe Leroy.Lcie: 255*fd1feadeSChristophe Leroy .long .Lcie_end - .Lcie_start 256*fd1feadeSChristophe Leroy.Lcie_start: 257*fd1feadeSChristophe Leroy .long 0 /* CIE ID */ 258*fd1feadeSChristophe Leroy .byte 1 /* Version number */ 259*fd1feadeSChristophe Leroy .string "zRS" /* NUL-terminated augmentation string */ 260*fd1feadeSChristophe Leroy .uleb128 4 /* Code alignment factor */ 261*fd1feadeSChristophe Leroy .sleb128 -4 /* Data alignment factor */ 262*fd1feadeSChristophe Leroy .byte 67 /* Return address register column, ap */ 263*fd1feadeSChristophe Leroy .uleb128 1 /* Augmentation value length */ 264*fd1feadeSChristophe Leroy .byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */ 265*fd1feadeSChristophe Leroy .byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */ 266*fd1feadeSChristophe Leroy .balign 4 267*fd1feadeSChristophe Leroy.Lcie_end: 268*fd1feadeSChristophe Leroy 269*fd1feadeSChristophe Leroy .long .Lfde0_end - .Lfde0_start 270*fd1feadeSChristophe Leroy.Lfde0_start: 271*fd1feadeSChristophe Leroy .long .Lfde0_start - .Lcie /* CIE pointer. */ 272*fd1feadeSChristophe Leroy .long .Lsig_start - . /* PC start, length */ 273*fd1feadeSChristophe Leroy .long .Lsig_end - .Lsig_start 274*fd1feadeSChristophe Leroy .uleb128 0 /* Augmentation */ 275*fd1feadeSChristophe Leroy EH_FRAME_GEN 276*fd1feadeSChristophe Leroy EH_FRAME_FP 277*fd1feadeSChristophe Leroy EH_FRAME_VMX 278*fd1feadeSChristophe Leroy .balign 4 279*fd1feadeSChristophe Leroy.Lfde0_end: 280*fd1feadeSChristophe Leroy 281*fd1feadeSChristophe Leroy/* We have a different stack layout for rt_sigreturn. */ 282*fd1feadeSChristophe Leroy#undef PTREGS 283*fd1feadeSChristophe Leroy#define PTREGS 64+16+128+20+28 284*fd1feadeSChristophe Leroy 285*fd1feadeSChristophe Leroy .long .Lfde1_end - .Lfde1_start 286*fd1feadeSChristophe Leroy.Lfde1_start: 287*fd1feadeSChristophe Leroy .long .Lfde1_start - .Lcie /* CIE pointer. */ 288*fd1feadeSChristophe Leroy .long .Lsigrt_start - . /* PC start, length */ 289*fd1feadeSChristophe Leroy .long .Lsigrt_end - .Lsigrt_start 290*fd1feadeSChristophe Leroy .uleb128 0 /* Augmentation */ 291*fd1feadeSChristophe Leroy EH_FRAME_GEN 292*fd1feadeSChristophe Leroy EH_FRAME_FP 293*fd1feadeSChristophe Leroy EH_FRAME_VMX 294*fd1feadeSChristophe Leroy .balign 4 295*fd1feadeSChristophe Leroy.Lfde1_end: 296