1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
17 #define SHMEM_VF_RESET_STATE ((u32)-1)
38  * direction: 0 for request, VF->PF; 1 for response, PF->VF.
67 #define SMC_LAST_DWORD (SMC_APERTURE_DWORDS - 1)
75 	/* Poll the hardware for the ownership bit. This should be pretty fast,  in mana_smc_poll_register()
87 		if (!(last_dword & BIT(31)))  in mana_smc_poll_register()
93 	return -ETIMEDOUT;  in mana_smc_poll_register()
99 	void __iomem *base = sc->base;  in mana_smc_read_response()
116 		dev_err(sc->dev, "Wrong SMC response 0x%x, type=%d, ver=%d\n",  in mana_smc_read_response()
118 		return -EPROTO;  in mana_smc_read_response()
123 		dev_err(sc->dev, "SMC operation failed: 0x%x\n", hdr.status);  in mana_smc_read_response()
124 		return -EPROTO;  in mana_smc_read_response()
133 	sc->dev = dev;  in mana_smc_init()
134 	sc->base = base;  in mana_smc_init()
153 	err = mana_smc_poll_register(sc->base, false);  in mana_smc_setup_hwc()
155 		dev_err(sc->dev, "Timeout when setting up HWC: %d\n", err);  in mana_smc_setup_hwc()
161 		return -EINVAL;  in mana_smc_setup_hwc()
164 		return -EINVAL;  in mana_smc_setup_hwc()
171 	 * 52-bit frame addresses are split into the lower 48 bits and upper  in mana_smc_setup_hwc()
172 	 * 4 bits. Lower 48 bits of 4 address are written sequentially from  in mana_smc_setup_hwc()
173 	 * the start of the 256-bit shared memory region followed by 16 bits  in mana_smc_setup_hwc()
176 	 * A 16 bit EQ vector number fills out the next-to-last 32-bit dword.  in mana_smc_setup_hwc()
178 	 * The final 32-bit dword is used for protocol control information as  in mana_smc_setup_hwc()
185 	/* EQ addr: low 48 bits of frame address */  in mana_smc_setup_hwc()
193 	/* CQ addr: low 48 bits of frame address */  in mana_smc_setup_hwc()
201 	/* RQ addr: low 48 bits of frame address */  in mana_smc_setup_hwc()
209 	/* SQ addr: low 48 bits of frame address */  in mana_smc_setup_hwc()
225 	/* 32-bit protocol header in final dword */  in mana_smc_setup_hwc()
229 	hdr->msg_type = SMC_MSG_TYPE_ESTABLISH_HWC;  in mana_smc_setup_hwc()
230 	hdr->msg_version = SMC_MSG_TYPE_ESTABLISH_HWC_VERSION;  in mana_smc_setup_hwc()
231 	hdr->direction = SMC_MSG_DIRECTION_REQUEST;  in mana_smc_setup_hwc()
232 	hdr->reset_vf = reset_vf;  in mana_smc_setup_hwc()
234 	/* Write 256-message buffer to shared memory (final 32-bit write  in mana_smc_setup_hwc()
235 	 * triggers HW to set possession bit to PF).  in mana_smc_setup_hwc()
239 		writel(*dword++, sc->base + i * SMC_BASIC_UNIT);  in mana_smc_setup_hwc()
249 		dev_err(sc->dev, "Error when setting up HWC: %d\n", err);  in mana_smc_setup_hwc()
262 	err = mana_smc_poll_register(sc->base, false);  in mana_smc_teardown_hwc()
264 		dev_err(sc->dev, "Timeout when tearing down HWC\n");  in mana_smc_teardown_hwc()
274 	/* Write message in high 32 bits of 256-bit shared memory, causing HW  in mana_smc_teardown_hwc()
275 	 * to set possession bit to PF.  in mana_smc_teardown_hwc()
277 	writel(hdr.as_uint32, sc->base + SMC_LAST_DWORD * SMC_BASIC_UNIT);  in mana_smc_teardown_hwc()
287 		dev_err(sc->dev, "Error when tearing down HWC: %d\n", err);  in mana_smc_teardown_hwc()