Lines Matching +full:48 +full:- +full:bit
1 // SPDX-License-Identifier: MIT
15 * DOC: Multi-Level LMTT Structure
17 * LMHAW (Local Memory Host Address Width) is 48 bit (256TB)
19 * LMGAW (Local Memory Guest Address Width) is 48 bit (256TB)
25 * +-----------+ +-----------+
27 * | | +-----------+ | |
29 * | | | | GDPA --> | PTE | => LMEM PF offset
33 * | | offset -> | PTE | ----------> +-----------+
34 * | | GAW-1:35 +===========+ / \.
36 * VFID --> | PDE | ---------> +-----------+ / \.
39 * +-----------+ <== [LMTT Directory Ptr] / \.
41 * / \ / / +-----------+-----------------+------+---+
42 * / /\ / | 31:HAW-16 | HAW-17:5 | 4:1 | 0 |
45 * / / +-----------+-----------------+------+---+
47 * +-----------+-----------------+------+---+
48 * | 63:HAW-12 | HAW-13:4 | 3:1 | 0 |
51 * +-----------+-----------------+------+---+
58 #define LMTT_ML_HAW 48 /* 256 TiB */
61 #define LMTT_ML_PDE_LMTT_PTR GENMASK_ULL(LMTT_ML_HAW - 13, 4)
62 #define LMTT_ML_PDE_VALID BIT(0)
65 #define LMTT_ML_PDE_L2_MAX_NUM BIT_ULL(LMTT_ML_HAW - 35)
67 #define LMTT_ML_PTE_MAX_NUM BIT(35 - ilog2(SZ_2M))
68 #define LMTT_ML_PTE_LMEM_PAGE GENMASK(LMTT_ML_HAW - 17, 5)
69 #define LMTT_ML_PTE_VALID BIT(0)
73 return 2; /* implementation is 0-based */ in lmtt_ml_root_pd_level()
82 BUILD_BUG_ON(LMTT_ML_HAW == 48 && LMTT_ML_PDE_L2_MAX_NUM != SZ_8K); in lmtt_ml_pte_num()
126 return addr & (LMTT_ML_PDE_L2_MAX_NUM - 1); in lmtt_ml_pte_index()
130 return addr & (LMTT_ML_PTE_MAX_NUM - 1); in lmtt_ml_pte_index()