17505576dSThomas Bogendoerfer /* SPDX-License-Identifier: GPL-2.0 */ 27505576dSThomas Bogendoerfer /* 37505576dSThomas Bogendoerfer * HEART chip definitions 47505576dSThomas Bogendoerfer * 57505576dSThomas Bogendoerfer * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org> 67505576dSThomas Bogendoerfer * 2009 Johannes Dickgreber <tanzy@gmx.de> 77505576dSThomas Bogendoerfer * 2007-2015 Joshua Kinard <kumba@gentoo.org> 87505576dSThomas Bogendoerfer */ 97505576dSThomas Bogendoerfer #ifndef __ASM_SGI_HEART_H 107505576dSThomas Bogendoerfer #define __ASM_SGI_HEART_H 117505576dSThomas Bogendoerfer 127505576dSThomas Bogendoerfer #include <linux/types.h> 137505576dSThomas Bogendoerfer #include <linux/time.h> 147505576dSThomas Bogendoerfer 157505576dSThomas Bogendoerfer /* 167505576dSThomas Bogendoerfer * There are 8 DIMM slots on an IP30 system 177505576dSThomas Bogendoerfer * board, which are grouped into four banks 187505576dSThomas Bogendoerfer */ 197505576dSThomas Bogendoerfer #define HEART_MEMORY_BANKS 4 207505576dSThomas Bogendoerfer 217505576dSThomas Bogendoerfer /* HEART can support up to four CPUs */ 227505576dSThomas Bogendoerfer #define HEART_MAX_CPUS 4 237505576dSThomas Bogendoerfer 247505576dSThomas Bogendoerfer #define HEART_XKPHYS_BASE ((void *)(IO_BASE | 0x000000000ff00000ULL)) 257505576dSThomas Bogendoerfer 267505576dSThomas Bogendoerfer /** 277505576dSThomas Bogendoerfer * struct ip30_heart_regs - struct that maps IP30 HEART registers. 287505576dSThomas Bogendoerfer * @mode: HEART_MODE - Purpose Unknown, machine reset called from here. 297505576dSThomas Bogendoerfer * @sdram_mode: HEART_SDRAM_MODE - purpose unknown. 307505576dSThomas Bogendoerfer * @mem_refresh: HEART_MEM_REF - purpose unknown. 317505576dSThomas Bogendoerfer * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown. 327505576dSThomas Bogendoerfer * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers. 337505576dSThomas Bogendoerfer * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers. 347505576dSThomas Bogendoerfer * @fc_mode: HEART_FC_MODE - Purpose Unknown, possibly for GFX flow control. 357505576dSThomas Bogendoerfer * @fc_timer_limit: HEART_FC_TIMER_LIMIT - purpose unknown. 367505576dSThomas Bogendoerfer * @fc_addr: HEART_FC0_ADDR, HEART_FC1_ADDR - purpose unknown. 377505576dSThomas Bogendoerfer * @fc_credit_cnt: HEART_FC0_CR_CNT, HEART_FC1_CR_CNT - purpose unknown. 387505576dSThomas Bogendoerfer * @fc_timer: HEART_FC0_TIMER, HEART_FC1_TIMER - purpose unknown. 397505576dSThomas Bogendoerfer * @status: HEART_STATUS - HEART status information. 407505576dSThomas Bogendoerfer * @bus_err_addr: HEART_BERR_ADDR - likely contains addr of recent SIGBUS. 417505576dSThomas Bogendoerfer * @bus_err_misc: HEART_BERR_MISC - purpose unknown. 427505576dSThomas Bogendoerfer * @mem_err_addr: HEART_MEMERR_ADDR - likely contains addr of recent mem err. 437505576dSThomas Bogendoerfer * @mem_err_data: HEART_MEMERR_DATA - purpose unknown. 447505576dSThomas Bogendoerfer * @piur_acc_err: HEART_PIUR_ACC_ERR - likely for access err to HEART regs. 457505576dSThomas Bogendoerfer * @mlan_clock_div: HEART_MLAN_CLK_DIV - MicroLAN clock divider. 467505576dSThomas Bogendoerfer * @mlan_ctrl: HEART_MLAN_CTL - MicroLAN control. 477505576dSThomas Bogendoerfer * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000. 487505576dSThomas Bogendoerfer * @undefined: Undefined/diag register, write to it triggers PIUR_ACC_ERR. 497505576dSThomas Bogendoerfer * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000. 507505576dSThomas Bogendoerfer * @imr: HEART_IMR0 to HEART_IMR3 - per-cpu interrupt mask register. 517505576dSThomas Bogendoerfer * @set_isr: HEART_SET_ISR - set interrupt status register. 527505576dSThomas Bogendoerfer * @clear_isr: HEART_CLR_ISR - clear interrupt status register. 537505576dSThomas Bogendoerfer * @isr: HEART_ISR - interrupt status register (read-only). 547505576dSThomas Bogendoerfer * @imsr: HEART_IMSR - purpose unknown. 557505576dSThomas Bogendoerfer * @cause: HEART_CAUSE - HEART cause information. 567505576dSThomas Bogendoerfer * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000. 577505576dSThomas Bogendoerfer * @count: HEART_COUNT - 52-bit counter. 587505576dSThomas Bogendoerfer * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000. 597505576dSThomas Bogendoerfer * @compare: HEART_COMPARE - 24-bit compare. 607505576dSThomas Bogendoerfer * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000. 617505576dSThomas Bogendoerfer * @trigger: HEART_TRIGGER - purpose unknown. 627505576dSThomas Bogendoerfer * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000. 637505576dSThomas Bogendoerfer * @cpuid: HEART_PRID - contains CPU ID of CPU currently accessing HEART. 647505576dSThomas Bogendoerfer * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000. 657505576dSThomas Bogendoerfer * @sync: HEART_SYNC - purpose unknown. 667505576dSThomas Bogendoerfer * 677505576dSThomas Bogendoerfer * HEART is the main system controller ASIC for IP30 system. It incorporates 687505576dSThomas Bogendoerfer * a memory controller, interrupt status/cause/set/clear management, basic 697505576dSThomas Bogendoerfer * timer with count/compare, and other functionality. For Linux, not all of 707505576dSThomas Bogendoerfer * HEART's functions are fully understood. 717505576dSThomas Bogendoerfer * 727505576dSThomas Bogendoerfer * Implementation note: All HEART registers are 64bits-wide, but the mem_cfg 737505576dSThomas Bogendoerfer * register only reports correct values if queried in 32bits. Hence the need 747505576dSThomas Bogendoerfer * for a union. Even though mem_cfg.l has 8 array slots, we only ever query 757505576dSThomas Bogendoerfer * up to 4 of those. IP30 has 8 DIMM slots arranged into 4 banks, w/ 2 DIMMs 767505576dSThomas Bogendoerfer * per bank. Each 32bit read accesses one of these banks. Perhaps HEART was 777505576dSThomas Bogendoerfer * designed to address up to 8 banks (16 DIMMs)? We may never know. 787505576dSThomas Bogendoerfer */ 797505576dSThomas Bogendoerfer struct ip30_heart_regs { /* 0x0ff00000 */ 807505576dSThomas Bogendoerfer u64 mode; /* + 0x00000 */ 817505576dSThomas Bogendoerfer /* Memory */ 827505576dSThomas Bogendoerfer u64 sdram_mode; /* + 0x00008 */ 837505576dSThomas Bogendoerfer u64 mem_refresh; /* + 0x00010 */ 847505576dSThomas Bogendoerfer u64 mem_req_arb; /* + 0x00018 */ 857505576dSThomas Bogendoerfer union { 867505576dSThomas Bogendoerfer u64 q[HEART_MEMORY_BANKS]; /* readq() */ 877505576dSThomas Bogendoerfer u32 l[HEART_MEMORY_BANKS * 2]; /* readl() */ 887505576dSThomas Bogendoerfer } mem_cfg; /* + 0x00020 */ 897505576dSThomas Bogendoerfer /* Flow control (gfx?) */ 907505576dSThomas Bogendoerfer u64 fc_mode; /* + 0x00040 */ 917505576dSThomas Bogendoerfer u64 fc_timer_limit; /* + 0x00048 */ 927505576dSThomas Bogendoerfer u64 fc_addr[2]; /* + 0x00050 */ 937505576dSThomas Bogendoerfer u64 fc_credit_cnt[2]; /* + 0x00060 */ 947505576dSThomas Bogendoerfer u64 fc_timer[2]; /* + 0x00070 */ 957505576dSThomas Bogendoerfer /* Status */ 967505576dSThomas Bogendoerfer u64 status; /* + 0x00080 */ 977505576dSThomas Bogendoerfer /* Bus error */ 987505576dSThomas Bogendoerfer u64 bus_err_addr; /* + 0x00088 */ 997505576dSThomas Bogendoerfer u64 bus_err_misc; /* + 0x00090 */ 1007505576dSThomas Bogendoerfer /* Memory error */ 1017505576dSThomas Bogendoerfer u64 mem_err_addr; /* + 0x00098 */ 1027505576dSThomas Bogendoerfer u64 mem_err_data; /* + 0x000a0 */ 1037505576dSThomas Bogendoerfer /* Misc */ 1047505576dSThomas Bogendoerfer u64 piur_acc_err; /* + 0x000a8 */ 1057505576dSThomas Bogendoerfer u64 mlan_clock_div; /* + 0x000b0 */ 1067505576dSThomas Bogendoerfer u64 mlan_ctrl; /* + 0x000b8 */ 1077505576dSThomas Bogendoerfer u64 __pad0[0x01e8]; /* + 0x000c0 + 0x0f40 */ 1087505576dSThomas Bogendoerfer /* Undefined */ 1097505576dSThomas Bogendoerfer u64 undefined; /* + 0x01000 */ 1107505576dSThomas Bogendoerfer u64 __pad1[0x1dff]; /* + 0x01008 + 0xeff8 */ 1117505576dSThomas Bogendoerfer /* Interrupts */ 1127505576dSThomas Bogendoerfer u64 imr[HEART_MAX_CPUS]; /* + 0x10000 */ 1137505576dSThomas Bogendoerfer u64 set_isr; /* + 0x10020 */ 1147505576dSThomas Bogendoerfer u64 clear_isr; /* + 0x10028 */ 1157505576dSThomas Bogendoerfer u64 isr; /* + 0x10030 */ 1167505576dSThomas Bogendoerfer u64 imsr; /* + 0x10038 */ 1177505576dSThomas Bogendoerfer u64 cause; /* + 0x10040 */ 1187505576dSThomas Bogendoerfer u64 __pad2[0x1ff7]; /* + 0x10048 + 0xffb8 */ 1197505576dSThomas Bogendoerfer /* Timer */ 1207505576dSThomas Bogendoerfer u64 count; /* + 0x20000 */ 1217505576dSThomas Bogendoerfer u64 __pad3[0x1fff]; /* + 0x20008 + 0xfff8 */ 1227505576dSThomas Bogendoerfer u64 compare; /* + 0x30000 */ 1237505576dSThomas Bogendoerfer u64 __pad4[0x1fff]; /* + 0x30008 + 0xfff8 */ 1247505576dSThomas Bogendoerfer u64 trigger; /* + 0x40000 */ 1257505576dSThomas Bogendoerfer u64 __pad5[0x1fff]; /* + 0x40008 + 0xfff8 */ 1267505576dSThomas Bogendoerfer /* Misc */ 1277505576dSThomas Bogendoerfer u64 cpuid; /* + 0x50000 */ 1287505576dSThomas Bogendoerfer u64 __pad6[0x1fff]; /* + 0x50008 + 0xfff8 */ 1297505576dSThomas Bogendoerfer u64 sync; /* + 0x60000 */ 1307505576dSThomas Bogendoerfer }; 1317505576dSThomas Bogendoerfer 1327505576dSThomas Bogendoerfer 1337505576dSThomas Bogendoerfer /* For timer-related bits. */ 1347505576dSThomas Bogendoerfer #define HEART_NS_PER_CYCLE 80 1357505576dSThomas Bogendoerfer #define HEART_CYCLES_PER_SEC (NSEC_PER_SEC / HEART_NS_PER_CYCLE) 1367505576dSThomas Bogendoerfer 1377505576dSThomas Bogendoerfer 1387505576dSThomas Bogendoerfer /* 1397505576dSThomas Bogendoerfer * XXX: Everything below this comment will either go away or be cleaned 1407505576dSThomas Bogendoerfer * up to fit in better with Linux. A lot of the bit definitions for 1417505576dSThomas Bogendoerfer * HEART were derived from IRIX's sys/RACER/heart.h header file. 1427505576dSThomas Bogendoerfer */ 1437505576dSThomas Bogendoerfer 1447505576dSThomas Bogendoerfer /* HEART Masks */ 1457505576dSThomas Bogendoerfer #define HEART_ATK_MASK 0x0007ffffffffffff /* HEART attack mask */ 1467505576dSThomas Bogendoerfer #define HEART_ACK_ALL_MASK 0xffffffffffffffff /* Ack everything */ 1477505576dSThomas Bogendoerfer #define HEART_CLR_ALL_MASK 0x0000000000000000 /* Clear all */ 1487505576dSThomas Bogendoerfer #define HEART_BR_ERR_MASK 0x7ff8000000000000 /* BRIDGE error mask */ 1497505576dSThomas Bogendoerfer #define HEART_CPU0_ERR_MASK 0x8ff8000000000000 /* CPU0 error mask */ 1507505576dSThomas Bogendoerfer #define HEART_CPU1_ERR_MASK 0x97f8000000000000 /* CPU1 error mask */ 1517505576dSThomas Bogendoerfer #define HEART_CPU2_ERR_MASK 0xa7f8000000000000 /* CPU2 error mask */ 1527505576dSThomas Bogendoerfer #define HEART_CPU3_ERR_MASK 0xc7f8000000000000 /* CPU3 error mask */ 1537505576dSThomas Bogendoerfer #define HEART_ERR_MASK 0x1ff /* HEART error mask */ 1547505576dSThomas Bogendoerfer #define HEART_ERR_MASK_START 51 /* HEART error start */ 1557505576dSThomas Bogendoerfer #define HEART_ERR_MASK_END 63 /* HEART error end */ 1567505576dSThomas Bogendoerfer 1577505576dSThomas Bogendoerfer /* Bits in the HEART_MODE register. */ 1587505576dSThomas Bogendoerfer #define HM_PROC_DISABLE_SHFT 60 1597505576dSThomas Bogendoerfer #define HM_PROC_DISABLE_MSK (0xfUL << HM_PROC_DISABLE_SHFT) 1607505576dSThomas Bogendoerfer #define HM_PROC_DISABLE(x) (0x1UL << (x) + HM_PROC_DISABLE_SHFT) 1617505576dSThomas Bogendoerfer #define HM_MAX_PSR (0x7UL << 57) 1627505576dSThomas Bogendoerfer #define HM_MAX_IOSR (0x7UL << 54) 1637505576dSThomas Bogendoerfer #define HM_MAX_PEND_IOSR (0x7UL << 51) 1647505576dSThomas Bogendoerfer #define HM_TRIG_SRC_SEL_MSK (0x7UL << 48) 1657505576dSThomas Bogendoerfer #define HM_TRIG_HEART_EXC (0x0UL << 48) 1667505576dSThomas Bogendoerfer #define HM_TRIG_REG_BIT (0x1UL << 48) 1677505576dSThomas Bogendoerfer #define HM_TRIG_SYSCLK (0x2UL << 48) 1687505576dSThomas Bogendoerfer #define HM_TRIG_MEMCLK_2X (0x3UL << 48) 1697505576dSThomas Bogendoerfer #define HM_TRIG_MEMCLK (0x4UL << 48) 1707505576dSThomas Bogendoerfer #define HM_TRIG_IOCLK (0x5UL << 48) 1717505576dSThomas Bogendoerfer #define HM_PIU_TEST_MODE (0xfUL << 40) 1727505576dSThomas Bogendoerfer #define HM_GP_FLAG_MSK (0xfUL << 36) 1737505576dSThomas Bogendoerfer #define HM_GP_FLAG(x) BIT((x) + 36) 1747505576dSThomas Bogendoerfer #define HM_MAX_PROC_HYST (0xfUL << 32) 1757505576dSThomas Bogendoerfer #define HM_LLP_WRST_AFTER_RST BIT(28) 1767505576dSThomas Bogendoerfer #define HM_LLP_LINK_RST BIT(27) 1777505576dSThomas Bogendoerfer #define HM_LLP_WARM_RST BIT(26) 1787505576dSThomas Bogendoerfer #define HM_COR_ECC_LCK BIT(25) 1797505576dSThomas Bogendoerfer #define HM_REDUCED_PWR BIT(24) 1807505576dSThomas Bogendoerfer #define HM_COLD_RST BIT(23) 1817505576dSThomas Bogendoerfer #define HM_SW_RST BIT(22) 1827505576dSThomas Bogendoerfer #define HM_MEM_FORCE_WR BIT(21) 1837505576dSThomas Bogendoerfer #define HM_DB_ERR_GEN BIT(20) 1847505576dSThomas Bogendoerfer #define HM_SB_ERR_GEN BIT(19) 1857505576dSThomas Bogendoerfer #define HM_CACHED_PIO_EN BIT(18) 1867505576dSThomas Bogendoerfer #define HM_CACHED_PROM_EN BIT(17) 1877505576dSThomas Bogendoerfer #define HM_PE_SYS_COR_ERE BIT(16) 1887505576dSThomas Bogendoerfer #define HM_GLOBAL_ECC_EN BIT(15) 1897505576dSThomas Bogendoerfer #define HM_IO_COH_EN BIT(14) 1907505576dSThomas Bogendoerfer #define HM_INT_EN BIT(13) 1917505576dSThomas Bogendoerfer #define HM_DATA_CHK_EN BIT(12) 1927505576dSThomas Bogendoerfer #define HM_REF_EN BIT(11) 1937505576dSThomas Bogendoerfer #define HM_BAD_SYSWR_ERE BIT(10) 1947505576dSThomas Bogendoerfer #define HM_BAD_SYSRD_ERE BIT(9) 1957505576dSThomas Bogendoerfer #define HM_SYSSTATE_ERE BIT(8) 1967505576dSThomas Bogendoerfer #define HM_SYSCMD_ERE BIT(7) 1977505576dSThomas Bogendoerfer #define HM_NCOR_SYS_ERE BIT(6) 1987505576dSThomas Bogendoerfer #define HM_COR_SYS_ERE BIT(5) 1997505576dSThomas Bogendoerfer #define HM_DATA_ELMNT_ERE BIT(4) 2007505576dSThomas Bogendoerfer #define HM_MEM_ADDR_PROC_ERE BIT(3) 2017505576dSThomas Bogendoerfer #define HM_MEM_ADDR_IO_ERE BIT(2) 2027505576dSThomas Bogendoerfer #define HM_NCOR_MEM_ERE BIT(1) 2037505576dSThomas Bogendoerfer #define HM_COR_MEM_ERE BIT(0) 2047505576dSThomas Bogendoerfer 2057505576dSThomas Bogendoerfer /* Bits in the HEART_MEM_REF register. */ 2067505576dSThomas Bogendoerfer #define HEART_MEMREF_REFS(x) ((0xfUL & (x)) << 16) 2077505576dSThomas Bogendoerfer #define HEART_MEMREF_PERIOD(x) ((0xffffUL & (x))) 2087505576dSThomas Bogendoerfer #define HEART_MEMREF_REFS_VAL HEART_MEMREF_REFS(8) 2097505576dSThomas Bogendoerfer #define HEART_MEMREF_PERIOD_VAL HEART_MEMREF_PERIOD(0x4000) 2107505576dSThomas Bogendoerfer #define HEART_MEMREF_VAL (HEART_MEMREF_REFS_VAL | \ 2117505576dSThomas Bogendoerfer HEART_MEMREF_PERIOD_VAL) 2127505576dSThomas Bogendoerfer 2137505576dSThomas Bogendoerfer /* Bits in the HEART_MEM_REQ_ARB register. */ 2147505576dSThomas Bogendoerfer #define HEART_MEMARB_IODIS (1 << 20) 2157505576dSThomas Bogendoerfer #define HEART_MEMARB_MAXPMWRQS (15 << 16) 2167505576dSThomas Bogendoerfer #define HEART_MEMARB_MAXPMRRQS (15 << 12) 2177505576dSThomas Bogendoerfer #define HEART_MEMARB_MAXPMRQS (15 << 8) 2187505576dSThomas Bogendoerfer #define HEART_MEMARB_MAXRRRQS (15 << 4) 2197505576dSThomas Bogendoerfer #define HEART_MEMARB_MAXGBRRQS (15) 2207505576dSThomas Bogendoerfer 2217505576dSThomas Bogendoerfer /* Bits in the HEART_MEMCFG<x> registers. */ 2227505576dSThomas Bogendoerfer #define HEART_MEMCFG_VALID 0x80000000 /* Bank is valid */ 2237505576dSThomas Bogendoerfer #define HEART_MEMCFG_DENSITY 0x01c00000 /* Mem density */ 2247505576dSThomas Bogendoerfer #define HEART_MEMCFG_SIZE_MASK 0x003f0000 /* Mem size mask */ 2257505576dSThomas Bogendoerfer #define HEART_MEMCFG_ADDR_MASK 0x000001ff /* Base addr mask */ 2267505576dSThomas Bogendoerfer #define HEART_MEMCFG_SIZE_SHIFT 16 /* Mem size shift */ 2277505576dSThomas Bogendoerfer #define HEART_MEMCFG_DENSITY_SHIFT 22 /* Density Shift */ 2287505576dSThomas Bogendoerfer #define HEART_MEMCFG_UNIT_SHIFT 25 /* Unit Shift, 32MB */ 2297505576dSThomas Bogendoerfer 2307505576dSThomas Bogendoerfer /* Bits in the HEART_STATUS register */ 2317505576dSThomas Bogendoerfer #define HEART_STAT_HSTL_SDRV BIT(14) 2327505576dSThomas Bogendoerfer #define HEART_STAT_FC_CR_OUT(x) BIT((x) + 12) 2337505576dSThomas Bogendoerfer #define HEART_STAT_DIR_CNNCT BIT(11) 2347505576dSThomas Bogendoerfer #define HEART_STAT_TRITON BIT(10) 2357505576dSThomas Bogendoerfer #define HEART_STAT_R4K BIT(9) 2367505576dSThomas Bogendoerfer #define HEART_STAT_BIG_ENDIAN BIT(8) 2377505576dSThomas Bogendoerfer #define HEART_STAT_PROC_SHFT 4 2387505576dSThomas Bogendoerfer #define HEART_STAT_PROC_MSK (0xfUL << HEART_STAT_PROC_SHFT) 2397505576dSThomas Bogendoerfer #define HEART_STAT_PROC_ACTIVE(x) (0x1UL << ((x) + HEART_STAT_PROC_SHFT)) 2407505576dSThomas Bogendoerfer #define HEART_STAT_WIDGET_ID 0xf 2417505576dSThomas Bogendoerfer 2427505576dSThomas Bogendoerfer /* Bits in the HEART_CAUSE register */ 2437505576dSThomas Bogendoerfer #define HC_PE_SYS_COR_ERR_MSK (0xfUL << 60) 2447505576dSThomas Bogendoerfer #define HC_PE_SYS_COR_ERR(x) BIT((x) + 60) 2457505576dSThomas Bogendoerfer #define HC_PIOWDB_OFLOW BIT(44) 2467505576dSThomas Bogendoerfer #define HC_PIORWRB_OFLOW BIT(43) 2477505576dSThomas Bogendoerfer #define HC_PIUR_ACC_ERR BIT(42) 2487505576dSThomas Bogendoerfer #define HC_BAD_SYSWR_ERR BIT(41) 2497505576dSThomas Bogendoerfer #define HC_BAD_SYSRD_ERR BIT(40) 2507505576dSThomas Bogendoerfer #define HC_SYSSTATE_ERR_MSK (0xfUL << 36) 2517505576dSThomas Bogendoerfer #define HC_SYSSTATE_ERR(x) BIT((x) + 36) 2527505576dSThomas Bogendoerfer #define HC_SYSCMD_ERR_MSK (0xfUL << 32) 2537505576dSThomas Bogendoerfer #define HC_SYSCMD_ERR(x) BIT((x) + 32) 2547505576dSThomas Bogendoerfer #define HC_NCOR_SYSAD_ERR_MSK (0xfUL << 28) 2557505576dSThomas Bogendoerfer #define HC_NCOR_SYSAD_ERR(x) BIT((x) + 28) 2567505576dSThomas Bogendoerfer #define HC_COR_SYSAD_ERR_MSK (0xfUL << 24) 2577505576dSThomas Bogendoerfer #define HC_COR_SYSAD_ERR(x) BIT((x) + 24) 2587505576dSThomas Bogendoerfer #define HC_DATA_ELMNT_ERR_MSK (0xfUL << 20) 2597505576dSThomas Bogendoerfer #define HC_DATA_ELMNT_ERR(x) BIT((x) + 20) 2607505576dSThomas Bogendoerfer #define HC_WIDGET_ERR BIT(16) 2617505576dSThomas Bogendoerfer #define HC_MEM_ADDR_ERR_PROC_MSK (0xfUL << 4) 2627505576dSThomas Bogendoerfer #define HC_MEM_ADDR_ERR_PROC(x) BIT((x) + 4) 2637505576dSThomas Bogendoerfer #define HC_MEM_ADDR_ERR_IO BIT(2) 2647505576dSThomas Bogendoerfer #define HC_NCOR_MEM_ERR BIT(1) 2657505576dSThomas Bogendoerfer #define HC_COR_MEM_ERR BIT(0) 2667505576dSThomas Bogendoerfer 267*7895d662SThomas Bogendoerfer /* 268*7895d662SThomas Bogendoerfer * HEART has 64 interrupt vectors available to it, subdivided into five 269*7895d662SThomas Bogendoerfer * priority levels. They are numbered 0 to 63. 270*7895d662SThomas Bogendoerfer */ 271*7895d662SThomas Bogendoerfer #define HEART_NUM_IRQS 64 272*7895d662SThomas Bogendoerfer 273*7895d662SThomas Bogendoerfer /* 274*7895d662SThomas Bogendoerfer * These are the five interrupt priority levels and their corresponding 275*7895d662SThomas Bogendoerfer * CPU IPx interrupt pins. 276*7895d662SThomas Bogendoerfer * 277*7895d662SThomas Bogendoerfer * Level 4 - Error Interrupts. 278*7895d662SThomas Bogendoerfer * Level 3 - HEART timer interrupt. 279*7895d662SThomas Bogendoerfer * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts. 280*7895d662SThomas Bogendoerfer * Level 1 - General device interrupts. 281*7895d662SThomas Bogendoerfer * Level 0 - General device GFX flow control interrupts. 282*7895d662SThomas Bogendoerfer */ 283*7895d662SThomas Bogendoerfer #define HEART_L4_INT_MASK 0xfff8000000000000ULL /* IP6 */ 284*7895d662SThomas Bogendoerfer #define HEART_L3_INT_MASK 0x0004000000000000ULL /* IP5 */ 285*7895d662SThomas Bogendoerfer #define HEART_L2_INT_MASK 0x0003ffff00000000ULL /* IP4 */ 286*7895d662SThomas Bogendoerfer #define HEART_L1_INT_MASK 0x00000000ffff0000ULL /* IP3 */ 287*7895d662SThomas Bogendoerfer #define HEART_L0_INT_MASK 0x000000000000ffffULL /* IP2 */ 288*7895d662SThomas Bogendoerfer 289*7895d662SThomas Bogendoerfer /* HEART L0 Interrupts (Low Priority) */ 290*7895d662SThomas Bogendoerfer #define HEART_L0_INT_GENERIC 0 291*7895d662SThomas Bogendoerfer #define HEART_L0_INT_FLOW_CTRL_HWTR_0 1 292*7895d662SThomas Bogendoerfer #define HEART_L0_INT_FLOW_CTRL_HWTR_1 2 293*7895d662SThomas Bogendoerfer 294*7895d662SThomas Bogendoerfer /* HEART L2 Interrupts (High Priority) */ 295*7895d662SThomas Bogendoerfer #define HEART_L2_INT_RESCHED_CPU_0 46 296*7895d662SThomas Bogendoerfer #define HEART_L2_INT_RESCHED_CPU_1 47 297*7895d662SThomas Bogendoerfer #define HEART_L2_INT_CALL_CPU_0 48 298*7895d662SThomas Bogendoerfer #define HEART_L2_INT_CALL_CPU_1 49 299*7895d662SThomas Bogendoerfer 300*7895d662SThomas Bogendoerfer /* HEART L3 Interrupts (Compare/Counter Timer) */ 301*7895d662SThomas Bogendoerfer #define HEART_L3_INT_TIMER 50 302*7895d662SThomas Bogendoerfer 303*7895d662SThomas Bogendoerfer /* HEART L4 Interrupts (Errors) */ 304*7895d662SThomas Bogendoerfer #define HEART_L4_INT_XWID_ERR_9 51 305*7895d662SThomas Bogendoerfer #define HEART_L4_INT_XWID_ERR_A 52 306*7895d662SThomas Bogendoerfer #define HEART_L4_INT_XWID_ERR_B 53 307*7895d662SThomas Bogendoerfer #define HEART_L4_INT_XWID_ERR_C 54 308*7895d662SThomas Bogendoerfer #define HEART_L4_INT_XWID_ERR_D 55 309*7895d662SThomas Bogendoerfer #define HEART_L4_INT_XWID_ERR_E 56 310*7895d662SThomas Bogendoerfer #define HEART_L4_INT_XWID_ERR_F 57 311*7895d662SThomas Bogendoerfer #define HEART_L4_INT_XWID_ERR_XBOW 58 312*7895d662SThomas Bogendoerfer #define HEART_L4_INT_CPU_BUS_ERR_0 59 313*7895d662SThomas Bogendoerfer #define HEART_L4_INT_CPU_BUS_ERR_1 60 314*7895d662SThomas Bogendoerfer #define HEART_L4_INT_CPU_BUS_ERR_2 61 315*7895d662SThomas Bogendoerfer #define HEART_L4_INT_CPU_BUS_ERR_3 62 316*7895d662SThomas Bogendoerfer #define HEART_L4_INT_HEART_EXCP 63 317*7895d662SThomas Bogendoerfer 3187505576dSThomas Bogendoerfer extern struct ip30_heart_regs __iomem *heart_regs; 3197505576dSThomas Bogendoerfer 3207505576dSThomas Bogendoerfer #define heart_read ____raw_readq 3217505576dSThomas Bogendoerfer #define heart_write ____raw_writeq 3227505576dSThomas Bogendoerfer 3237505576dSThomas Bogendoerfer #endif /* __ASM_SGI_HEART_H */ 324