Lines Matching +full:48 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32 * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33 * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
34 * @fc_mode: HEART_FC_MODE - Purpose Unknown, possibly for GFX flow control.
35 * @fc_timer_limit: HEART_FC_TIMER_LIMIT - purpose unknown.
36 * @fc_addr: HEART_FC0_ADDR, HEART_FC1_ADDR - purpose unknown.
37 * @fc_credit_cnt: HEART_FC0_CR_CNT, HEART_FC1_CR_CNT - purpose unknown.
38 * @fc_timer: HEART_FC0_TIMER, HEART_FC1_TIMER - purpose unknown.
39 * @status: HEART_STATUS - HEART status information.
40 * @bus_err_addr: HEART_BERR_ADDR - likely contains addr of recent SIGBUS.
41 * @bus_err_misc: HEART_BERR_MISC - purpose unknown.
42 * @mem_err_addr: HEART_MEMERR_ADDR - likely contains addr of recent mem err.
43 * @mem_err_data: HEART_MEMERR_DATA - purpose unknown.
44 * @piur_acc_err: HEART_PIUR_ACC_ERR - likely for access err to HEART regs.
45 * @mlan_clock_div: HEART_MLAN_CLK_DIV - MicroLAN clock divider.
46 * @mlan_ctrl: HEART_MLAN_CTL - MicroLAN control.
47 * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
49 * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
50 * @imr: HEART_IMR0 to HEART_IMR3 - per-cpu interrupt mask register.
51 * @set_isr: HEART_SET_ISR - set interrupt status register.
52 * @clear_isr: HEART_CLR_ISR - clear interrupt status register.
53 * @isr: HEART_ISR - interrupt status register (read-only).
54 * @imsr: HEART_IMSR - purpose unknown.
55 * @cause: HEART_CAUSE - HEART cause information.
56 * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
57 * @count: HEART_COUNT - 52-bit counter.
58 * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
59 * @compare: HEART_COMPARE - 24-bit compare.
60 * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
61 * @trigger: HEART_TRIGGER - purpose unknown.
62 * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
63 * @cpuid: HEART_PRID - contains CPU ID of CPU currently accessing HEART.
64 * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
65 * @sync: HEART_SYNC - purpose unknown.
72 * Implementation note: All HEART registers are 64bits-wide, but the mem_cfg
76 * per bank. Each 32bit read accesses one of these banks. Perhaps HEART was
133 /* For timer-related bits. */
140 * up to fit in better with Linux. A lot of the bit definitions for
164 #define HM_TRIG_SRC_SEL_MSK (0x7UL << 48)
165 #define HM_TRIG_HEART_EXC (0x0UL << 48)
166 #define HM_TRIG_REG_BIT (0x1UL << 48)
167 #define HM_TRIG_SYSCLK (0x2UL << 48)
168 #define HM_TRIG_MEMCLK_2X (0x3UL << 48)
169 #define HM_TRIG_MEMCLK (0x4UL << 48)
170 #define HM_TRIG_IOCLK (0x5UL << 48)
173 #define HM_GP_FLAG(x) BIT((x) + 36)
175 #define HM_LLP_WRST_AFTER_RST BIT(28)
176 #define HM_LLP_LINK_RST BIT(27)
177 #define HM_LLP_WARM_RST BIT(26)
178 #define HM_COR_ECC_LCK BIT(25)
179 #define HM_REDUCED_PWR BIT(24)
180 #define HM_COLD_RST BIT(23)
181 #define HM_SW_RST BIT(22)
182 #define HM_MEM_FORCE_WR BIT(21)
183 #define HM_DB_ERR_GEN BIT(20)
184 #define HM_SB_ERR_GEN BIT(19)
185 #define HM_CACHED_PIO_EN BIT(18)
186 #define HM_CACHED_PROM_EN BIT(17)
187 #define HM_PE_SYS_COR_ERE BIT(16)
188 #define HM_GLOBAL_ECC_EN BIT(15)
189 #define HM_IO_COH_EN BIT(14)
190 #define HM_INT_EN BIT(13)
191 #define HM_DATA_CHK_EN BIT(12)
192 #define HM_REF_EN BIT(11)
193 #define HM_BAD_SYSWR_ERE BIT(10)
194 #define HM_BAD_SYSRD_ERE BIT(9)
195 #define HM_SYSSTATE_ERE BIT(8)
196 #define HM_SYSCMD_ERE BIT(7)
197 #define HM_NCOR_SYS_ERE BIT(6)
198 #define HM_COR_SYS_ERE BIT(5)
199 #define HM_DATA_ELMNT_ERE BIT(4)
200 #define HM_MEM_ADDR_PROC_ERE BIT(3)
201 #define HM_MEM_ADDR_IO_ERE BIT(2)
202 #define HM_NCOR_MEM_ERE BIT(1)
203 #define HM_COR_MEM_ERE BIT(0)
231 #define HEART_STAT_HSTL_SDRV BIT(14)
232 #define HEART_STAT_FC_CR_OUT(x) BIT((x) + 12)
233 #define HEART_STAT_DIR_CNNCT BIT(11)
234 #define HEART_STAT_TRITON BIT(10)
235 #define HEART_STAT_R4K BIT(9)
236 #define HEART_STAT_BIG_ENDIAN BIT(8)
244 #define HC_PE_SYS_COR_ERR(x) BIT((x) + 60)
245 #define HC_PIOWDB_OFLOW BIT(44)
246 #define HC_PIORWRB_OFLOW BIT(43)
247 #define HC_PIUR_ACC_ERR BIT(42)
248 #define HC_BAD_SYSWR_ERR BIT(41)
249 #define HC_BAD_SYSRD_ERR BIT(40)
251 #define HC_SYSSTATE_ERR(x) BIT((x) + 36)
253 #define HC_SYSCMD_ERR(x) BIT((x) + 32)
255 #define HC_NCOR_SYSAD_ERR(x) BIT((x) + 28)
257 #define HC_COR_SYSAD_ERR(x) BIT((x) + 24)
259 #define HC_DATA_ELMNT_ERR(x) BIT((x) + 20)
260 #define HC_WIDGET_ERR BIT(16)
262 #define HC_MEM_ADDR_ERR_PROC(x) BIT((x) + 4)
263 #define HC_MEM_ADDR_ERR_IO BIT(2)
264 #define HC_NCOR_MEM_ERR BIT(1)
265 #define HC_COR_MEM_ERR BIT(0)
277 * Level 4 - Error Interrupts.
278 * Level 3 - HEART timer interrupt.
279 * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
280 * Level 1 - General device interrupts.
281 * Level 0 - General device GFX flow control interrupts.
297 #define HEART_L2_INT_CALL_CPU_0 48