Home
last modified time | relevance | path

Searched +full:16 +full:bit (Results 1 – 25 of 1443) sorted by relevance

12345678910>>...58

/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DMSP430Target.def203 // With 16-bit hardware multiplier
204 MSP430_MCU_FEAT("msp430c336", "16bit")
205 MSP430_MCU_FEAT("msp430c337", "16bit")
206 MSP430_MCU_FEAT("msp430cg4616", "16bit")
207 MSP430_MCU_FEAT("msp430cg4617", "16bit")
208 MSP430_MCU_FEAT("msp430cg4618", "16bit")
209 MSP430_MCU_FEAT("msp430cg4619", "16bit")
210 MSP430_MCU_FEAT("msp430e337", "16bit")
211 MSP430_MCU_FEAT("msp430f147", "16bit")
212 MSP430_MCU_FEAT("msp430f148", "16bit")
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Dreg.h9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
24 #define B_AX_XTAL_OFF_A_DIE BIT(22)
25 #define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(1
[all...]
H A Dtxrx.h65 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
66 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
67 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
68 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
70 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
71 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
77 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
83 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
88 #define RTW89_TXWD_BODY3_BK BIT(13)
89 #define RTW89_TXWD_BODY3_AGG_EN BIT(1
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRFixupKinds.h27 /// A 32-bit AVR fixup.
30 /// A 7-bit PC-relative fixup for the family of conditional
31 /// branches which take 7-bit targets (BRNE,BRGT,etc).
33 /// A 12-bit PC-relative fixup for the family of branches
34 /// which take 12-bit targets (RJMP,RCALL,etc).
39 /// aligned to 2 bytes, so the 0'th bit is always 0.
43 /// A 16-bit address.
45 /// A 16-bit progra
[all...]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h40 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
41 #define MT_TX_FREE_PAIR BIT(31)
47 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
56 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
62 #define MT_TXD2_FIX_RATE BIT(31)
[all …]
H A Dmt76_connac3_mac.h25 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
30 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
34 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
42 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
[all …]
H A Dmt76x02_regs.h15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
[all …]
H A Dregs.h40 #define MT_TOP_3NSS BIT(24)
43 #define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
75 #define MT_PDMA_AXI_SLPPROT_RDY BIT(16)
78 #define MT_PDMA_TX_IDX_BUSY BIT(2)
79 #define MT_PDMA_BUSY_IDX BIT(31)
85 #define MT7663_MCU_PCIE_REMAP_2_BASE GENMASK(31, 16)
93 #define MT_CFG_LPCR_HOST_FW_OWN BIT(0)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
[all …]
H A Dmac.h9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
[all …]
/freebsd/sys/dev/sfxge/common/
H A Defx_regs_pci.h41 * PC_VEND_ID_REG(16bit):
49 #define PCRF_AZ_VEND_ID_WIDTH 16
52 * PC_DEV_ID_REG(16bit):
60 #define PCRF_AZ_DEV_ID_WIDTH 16
63 * PC_CMD_REG(16bit):
94 * PC_STAT_REG(16bit):
125 * PC_REV_ID_REG(8bit):
136 * PC_CC_REG(24bit):
143 #define PCRF_AZ_BASE_CC_LBN 16
151 * PC_CACHE_LSIZE_REG(8bit):
[all …]
H A Defx_regs.h48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
69 #define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
78 #define FRF_AB_EE_VPD_LENGTH_LBN 16
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
150 #define FRF_AB_PCIE_RXEQCTL_L_LBN 16
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
196 #define FRF_AB_PCIE_DEQ4_LBN 16
[all …]
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Davxvnniint16intrin.h26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
46 /// A 128-bit vector of [4 x int].
63 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
64 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
[all …]
H A Davxneconvertintrin.h28 /// Convert scalar BF16 (16-bit) floating-point element
30 /// single-precision (32-bit) floating-point, broadcast it to packed
31 /// single-precision (32-bit) floating-point elements, and store the results in
43 /// A pointer to a 16-bit memory location. The address of the memory
46 /// A 128-bit vector of [4 x float].
61 /// Convert scalar BF16 (16-bit) floating-point element
63 /// single-precision (32-bit) floating-point, broadcast it to packed
64 /// single-precision (32-bit) floating-point elements, and store the results in
76 /// A pointer to a 16-bit memory location. The address of the memory
79 /// A 256-bit vector of [8 x float].
[all …]
H A Df16cintrin.h23 /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
28 /// Converts a 16-bit half-precision float value into a 32-bit float
36 /// A 16-bit half-precision float value.
37 /// \returns The converted 32-bit float value.
46 /// Converts a 32-bit single-precision float value to a 16-bit
58 /// A 32-bit single-precision float value to be converted to a 16-bit
67 /// \returns The converted 16-bit half-precision float value.
72 /// Converts a 128-bit vector containing 32-bit float values into a
73 /// 128-bit vector containing 16-bit half-precision float values.
84 /// A 128-bit vector containing 32-bit float values.
[all …]
H A Dmmintrin.h42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
59 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
67 /// A 64-bit integer vector.
68 /// \returns A 32-bit signed integer value containing the lower 32 bits of the
76 /// Casts a 64-bit signed integer value into a 64-bit integer vector.
83 /// A 64-bit signed integer.
84 /// \returns A 64-bit integer vector containing the same bitwise pattern as the
[all …]
/freebsd/sys/dev/qat/include/
H A Dicp_qat_hw.h49 ICP_QAT_HW_AUTH_RESERVED_2 = 16,
83 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
84 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
85 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
86 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
87 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
88 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
89 ICP_ACCEL_CAPABILITIES_DEPRECATED = BIT(6),
90 ICP_ACCEL_CAPABILITIES_RAND = BIT(7),
91 ICP_ACCEL_CAPABILITIES_ZUC = BIT(8),
[all …]
/freebsd/sys/dev/msk/
H A Dif_mskreg.h175 #define BIT_16 (1 << 16)
208 #define SHIFT16(x) ((x) << 16)
229 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
230 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
231 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
232 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
233 #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
234 #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
235 #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
236 #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
[all …]
/freebsd/contrib/wpa/src/crypto/
H A Dmilenage.c27 * @opc: OPc = 128-bit value derived from OP and K
28 * @k: K = 128-bit subscriber key
29 * @_rand: RAND = 128-bit random challenge
30 * @sqn: SQN = 48-bit sequence number
31 * @amf: AMF = 16-bit authentication management field
32 * @mac_a: Buffer for MAC-A = 64-bit network authentication code, or %NULL
33 * @mac_s: Buffer for MAC-S = 64-bit resync authentication code, or %NULL
39 u8 tmp1[16], tmp2[16], tmp3[16]; in milenage_f1()
43 for (i = 0; i < 16; i++) in milenage_f1()
56 for (i = 0; i < 16; i++) in milenage_f1()
[all …]
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_reg.h20 * Register manipulation macros that expect bit field defines
28 #define BIT(_n) (1UL << (_n)) macro
51 #define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
101 #define AR40XX_MODULE_EN_MIB BIT(0)
104 #define AR40XX_MIB_BUSY BIT(17)
105 #define AR40XX_MIB_CPU_KEEP BIT(20)
112 #define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
123 #define AR40XX_REG_SW_MAC_ADDR1_BYTE1 BITS(16, 8)
124 #define AR40XX_REG_SW_MAC_ADDR1_BYTE1_S 16
136 #define AR40XX_PORT_TX_EN BIT(2)
[all …]
/freebsd/sys/dev/stge/
H A Dif_stgereg.h77 * Note that while DMA addresses are all in 64-bit fields, only
132 #define TFD_WordAlign(x) ((x) << 16)
203 #define DMAC_RxEarlyDisable (1U << 16)
216 #define STGE_TxDMABurstThresh 0x18 /* 8-bit */
218 #define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */
220 #define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */
226 #define STGE_RxDMABurstThresh 0x24 /* 8-bit */
228 #define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */
230 #define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */
235 #define RDIC_RxDMAWaitTime(x) ((x) << 16)
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8723d.h20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h139 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
140 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
141 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
142 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
149 #define MT_PLE_HOST_RPT0_TX_LATENCY BIT(3)
174 #define MT_MDP_DCR0_DAMSDU_EN BIT(15)
180 #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2)
201 #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)
210 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
215 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
[all …]
/freebsd/lib/libc/arm/string/
H A Dmemcpy.S176 /* At least 16 bytes remaining */
259 mov r4, ip, lsr #16
265 orr r4, r4, r5, lsl #16
266 mov r5, r5, lsr #16
267 orr r5, r5, r6, lsl #16
268 mov r6, r6, lsr #16
269 orr r6, r6, r7, lsl #16
270 mov r7, r7, lsr #16
271 orr r7, r7, ip, lsl #16
288 mov r4, ip, lsr #16
[all …]

12345678910>>...58