Lines Matching +full:16 +full:bit
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
52 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)
56 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)
64 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
67 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
71 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
75 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
77 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
81 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
85 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
91 #define RTW89_C2HREG_PS_LEAVE_ACK_MACID GENMASK(31, 16)
105 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
107 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
109 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
111 #define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)
421 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
425 #define RTW89_H2C_RA_W0_DCM BIT(16)
426 #define RTW89_H2C_RA_W0_ER BIT(17)
428 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
429 #define RTW89_H2C_RA_W0_SGI BIT(21)
430 #define RTW89_H2C_RA_W0_LDPC BIT(22)
431 #define RTW89_H2C_RA_W0_STBC BIT(23)
434 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
435 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
438 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
440 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
441 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
442 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
443 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
445 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
458 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
473 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_SEC_LEN()
483 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); in RTW89_SET_FWCMD_SEC_EXT_KEY()
488 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); in RTW89_SET_FWCMD_SEC_SPP_MODE()
518 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); in RTW89_SET_EDCA_BAND()
523 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); in RTW89_SET_EDCA_WMM()
535 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
566 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
567 #define FWSECTION_HDR_W1_REDL BIT(29)
585 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
588 #define FW_HDR_W3_LEN GENMASK(23, 16)
592 #define FW_HDR_W4_HOUR GENMASK(23, 16)
597 #define FW_HDR_W7_DYN_HDR BIT(16)
612 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
613 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
637 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
640 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
644 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
647 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
649 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
651 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
706 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); in SET_CTRL_INFO_OPERATION()
715 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
718 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); in SET_CMC_TBL_FORCE_TXOP()
720 BIT(9)); in SET_CMC_TBL_FORCE_TXOP()
736 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
739 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); in SET_CMC_TBL_DARF_TC_INDEX()
741 BIT(15)); in SET_CMC_TBL_DARF_TC_INDEX()
746 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); in SET_CMC_TBL_ARFR_CTRL()
748 GENMASK(19, 16)); in SET_CMC_TBL_ARFR_CTRL()
750 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
753 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); in SET_CMC_TBL_ACQ_RPT_EN()
755 BIT(20)); in SET_CMC_TBL_ACQ_RPT_EN()
757 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
760 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); in SET_CMC_TBL_MGQ_RPT_EN()
762 BIT(21)); in SET_CMC_TBL_MGQ_RPT_EN()
764 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
767 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); in SET_CMC_TBL_ULQ_RPT_EN()
769 BIT(22)); in SET_CMC_TBL_ULQ_RPT_EN()
771 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
774 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); in SET_CMC_TBL_TWTQ_RPT_EN()
776 BIT(23)); in SET_CMC_TBL_TWTQ_RPT_EN()
778 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
781 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); in SET_CMC_TBL_DISRTSFB()
783 BIT(25)); in SET_CMC_TBL_DISRTSFB()
785 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
788 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); in SET_CMC_TBL_DISDATAFB()
790 BIT(26)); in SET_CMC_TBL_DISDATAFB()
792 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
795 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); in SET_CMC_TBL_TRYRATE()
797 BIT(27)); in SET_CMC_TBL_TRYRATE()
813 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
816 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); in SET_CMC_TBL_AMPDU_TIME_SEL()
818 BIT(9)); in SET_CMC_TBL_AMPDU_TIME_SEL()
820 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
823 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); in SET_CMC_TBL_AMPDU_LEN_SEL()
825 BIT(10)); in SET_CMC_TBL_AMPDU_LEN_SEL()
827 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
830 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); in SET_CMC_TBL_RTS_TXCNT_LMT_SEL()
832 BIT(11)); in SET_CMC_TBL_RTS_TXCNT_LMT_SEL()
844 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); in SET_CMC_TBL_RTSRATE()
846 GENMASK(24, 16)); in SET_CMC_TBL_RTSRATE()
848 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
851 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); in SET_CMC_TBL_VCS_STBC()
853 BIT(27)); in SET_CMC_TBL_VCS_STBC()
869 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
872 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); in SET_CMC_TBL_DATA_TXCNT_LMT_SEL()
874 BIT(6)); in SET_CMC_TBL_DATA_TXCNT_LMT_SEL()
876 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
879 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); in SET_CMC_TBL_MAX_AGG_NUM_SEL()
881 BIT(7)); in SET_CMC_TBL_MAX_AGG_NUM_SEL()
883 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
886 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); in SET_CMC_TBL_RTS_EN()
888 BIT(8)); in SET_CMC_TBL_RTS_EN()
890 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
893 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); in SET_CMC_TBL_CTS2SELF_EN()
895 BIT(9)); in SET_CMC_TBL_CTS2SELF_EN()
904 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
907 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); in SET_CMC_TBL_HW_RTS_EN()
909 BIT(12)); in SET_CMC_TBL_HW_RTS_EN()
921 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); in SET_CMC_TBL_AMPDU_MAX_LEN()
923 GENMASK(26, 16)); in SET_CMC_TBL_AMPDU_MAX_LEN()
925 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
928 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); in SET_CMC_TBL_UL_MU_DIS()
930 BIT(27)); in SET_CMC_TBL_UL_MU_DIS()
956 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); in SET_CMC_TBL_VO_LFTIME_SEL()
958 GENMASK(18, 16)); in SET_CMC_TBL_VO_LFTIME_SEL()
995 #define SET_CMC_TBL_MASK_BMC BIT(0)
998 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); in SET_CMC_TBL_BMC()
1000 BIT(3)); in SET_CMC_TBL_BMC()
1009 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
1012 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); in SET_CMC_TBL_NAVUSEHDR()
1014 BIT(8)); in SET_CMC_TBL_NAVUSEHDR()
1023 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
1026 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); in SET_CMC_TBL_DATA_DCM()
1028 BIT(12)); in SET_CMC_TBL_DATA_DCM()
1030 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
1033 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); in SET_CMC_TBL_DATA_ER()
1035 BIT(13)); in SET_CMC_TBL_DATA_ER()
1037 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
1040 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); in SET_CMC_TBL_DATA_LDPC()
1042 BIT(14)); in SET_CMC_TBL_DATA_LDPC()
1044 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
1047 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); in SET_CMC_TBL_DATA_STBC()
1049 BIT(15)); in SET_CMC_TBL_DATA_STBC()
1051 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
1054 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); in SET_CMC_TBL_A_CTRL_BQR()
1056 BIT(16)); in SET_CMC_TBL_A_CTRL_BQR()
1058 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
1061 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); in SET_CMC_TBL_A_CTRL_UPH()
1063 BIT(17)); in SET_CMC_TBL_A_CTRL_UPH()
1065 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
1068 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); in SET_CMC_TBL_A_CTRL_BSR()
1070 BIT(18)); in SET_CMC_TBL_A_CTRL_BSR()
1072 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
1075 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); in SET_CMC_TBL_A_CTRL_CAS()
1077 BIT(19)); in SET_CMC_TBL_A_CTRL_CAS()
1079 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
1082 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); in SET_CMC_TBL_DATA_BW_ER()
1084 BIT(20)); in SET_CMC_TBL_DATA_BW_ER()
1086 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
1089 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); in SET_CMC_TBL_LSIG_TXOP_EN()
1091 BIT(21)); in SET_CMC_TBL_LSIG_TXOP_EN()
1093 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
1096 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); in SET_CMC_TBL_CTRL_CNT_VLD()
1098 BIT(27)); in SET_CMC_TBL_CTRL_CNT_VLD()
1114 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
1117 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); in SET_CMC_TBL_ALL_ACK_SUPPORT()
1119 BIT(12)); in SET_CMC_TBL_ALL_ACK_SUPPORT()
1121 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
1124 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); in SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT()
1126 BIT(13)); in SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT()
1131 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); in SET_CMC_TBL_NTX_PATH_EN()
1133 GENMASK(19, 16)); in SET_CMC_TBL_NTX_PATH_EN()
1163 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1166 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); in SET_CMC_TBL_ANTSEL_A()
1168 BIT(28)); in SET_CMC_TBL_ANTSEL_A()
1170 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1173 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); in SET_CMC_TBL_ANTSEL_B()
1175 BIT(29)); in SET_CMC_TBL_ANTSEL_B()
1177 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1180 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); in SET_CMC_TBL_ANTSEL_C()
1182 BIT(30)); in SET_CMC_TBL_ANTSEL_C()
1184 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1187 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); in SET_CMC_TBL_ANTSEL_D()
1189 BIT(31)); in SET_CMC_TBL_ANTSEL_D()
1231 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); in SET_CMC_TBL_PAID()
1233 GENMASK(16, 8)); in SET_CMC_TBL_PAID()
1235 #define SET_CMC_TBL_MASK_ULDL BIT(0)
1238 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); in SET_CMC_TBL_ULDL()
1240 BIT(17)); in SET_CMC_TBL_ULDL()
1280 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, in SET_CMC_TBL_NC()
1287 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, in SET_CMC_TBL_NR()
1294 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, in SET_CMC_TBL_NG()
1301 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, in SET_CMC_TBL_CB()
1308 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, in SET_CMC_TBL_CS()
1311 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1314 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); in SET_CMC_TBL_CSI_TXBF_EN()
1315 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, in SET_CMC_TBL_CSI_TXBF_EN()
1316 BIT(12)); in SET_CMC_TBL_CSI_TXBF_EN()
1318 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1321 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); in SET_CMC_TBL_CSI_STBC_EN()
1322 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, in SET_CMC_TBL_CSI_STBC_EN()
1323 BIT(13)); in SET_CMC_TBL_CSI_STBC_EN()
1325 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1328 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); in SET_CMC_TBL_CSI_LDPC_EN()
1329 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, in SET_CMC_TBL_CSI_LDPC_EN()
1330 BIT(14)); in SET_CMC_TBL_CSI_LDPC_EN()
1332 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1335 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); in SET_CMC_TBL_CSI_PARA_EN()
1336 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, in SET_CMC_TBL_CSI_PARA_EN()
1337 BIT(15)); in SET_CMC_TBL_CSI_PARA_EN()
1342 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); in SET_CMC_TBL_CSI_FIX_RATE()
1343 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, in SET_CMC_TBL_CSI_FIX_RATE()
1344 GENMASK(24, 16)); in SET_CMC_TBL_CSI_FIX_RATE()
1350 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, in SET_CMC_TBL_CSI_GI_LTF()
1357 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, in SET_CMC_TBL_NOMINAL_PKT_PADDING160()
1365 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, in SET_CMC_TBL_CSI_BW()
1406 #define CCTLINFO_G7_C0_OP BIT(7)
1410 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1411 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1412 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1413 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1414 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1415 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1416 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1417 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1418 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1419 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1420 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1425 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1429 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1430 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1431 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1432 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1434 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1436 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1437 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1438 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1443 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1445 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1446 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1450 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1451 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1452 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1453 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1456 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1458 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1459 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1460 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1461 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1462 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1463 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1464 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1465 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1473 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1475 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1478 #define CCTLINFO_G7_W6_ULDL BIT(31)
1479 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1485 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1486 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1487 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1488 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1491 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1492 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1493 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1494 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1495 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1496 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1497 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1498 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1509 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1520 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1527 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1533 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1534 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1535 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1536 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1574 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1582 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1588 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1589 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1590 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1591 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1594 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1596 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1598 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1600 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1602 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1603 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1612 #define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13)
1634 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1635 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1637 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1638 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1640 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1647 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1649 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1652 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1653 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1654 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1655 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1664 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1678 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); in SET_GENERAL_PKT_PSPOLL_ID()
1721 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1722 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1726 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1729 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1730 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1738 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1739 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1742 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1745 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1746 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1747 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1756 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1770 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); in SET_LPS_PARM_RLBM()
1785 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); in SET_LPS_PARM_VOUAPSD()
1790 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); in SET_LPS_PARM_VIUAPSD()
1795 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); in SET_LPS_PARM_BEUAPSD()
1800 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); in SET_LPS_PARM_BKUAPSD()
1856 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_PKT_DROP_BAND()
1906 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16)); in RTW89_SET_KEEP_ALIVE_PERIOD()
1916 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); in RTW89_SET_DISCONNECT_DETECT_ENABLE()
1921 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); in RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN()
1926 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); in RTW89_SET_DISCONNECT_DETECT_DISCONNECT()
1936 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); in RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD()
1954 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1955 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1956 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1957 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1959 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1962 #define RTW89_MAX_SUPPORT_NL_NUM 16
1976 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1977 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1982 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); in RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE()
1987 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); in RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE()
1992 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); in RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE()
1997 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); in RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE()
2002 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); in RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE()
2007 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); in RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE()
2012 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); in RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE()
2017 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); in RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE()
2027 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); in RTW89_SET_WOW_CAM_UPD_R_W()
2062 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); in RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH()
2067 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); in RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR()
2072 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); in RTW89_SET_WOW_CAM_UPD_UC()
2077 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); in RTW89_SET_WOW_CAM_UPD_MC()
2082 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); in RTW89_SET_WOW_CAM_UPD_BC()
2087 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); in RTW89_SET_WOW_CAM_UPD_VALID()
2096 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2097 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2098 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2099 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2100 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2101 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2112 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2113 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2114 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2282 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2283 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2287 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2288 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2289 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2292 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2293 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2294 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2295 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2296 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2315 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ROLE_NONE()
2320 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); in RTW89_SET_FWCMD_CXROLE_ROLE_STA()
2325 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); in RTW89_SET_FWCMD_CXROLE_ROLE_AP()
2330 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); in RTW89_SET_FWCMD_CXROLE_ROLE_VAP()
2335 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); in RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC()
2340 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); in RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER()
2345 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); in RTW89_SET_FWCMD_CXROLE_ROLE_MESH()
2350 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); in RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR()
2355 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); in RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV()
2360 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); in RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC()
2365 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); in RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO()
2370 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); in RTW89_SET_FWCMD_CXROLE_ROLE_NAN()
2375 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED()
2385 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); in RTW89_SET_FWCMD_CXROLE_ACT_PHY()
2390 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); in RTW89_SET_FWCMD_CXROLE_ACT_NOA()
2400 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS()
2435 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE()
2445 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2()
2455 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); in RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2()
2460 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); in RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2()
2470 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2()
2505 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_DBCC_EN()
2510 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); in RTW89_SET_FWCMD_CXROLE_DBCC_CHG()
2520 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); in RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG()
2525 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); in RTW89_SET_FWCMD_CXCTRL_MANUAL()
2530 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); in RTW89_SET_FWCMD_CXCTRL_IGNORE_BT()
2535 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); in RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN()
2610 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0)); in RTW89_SET_FWCMD_CXTRX_RXRATE()
2665 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); in RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH()
2680 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2685 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2686 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2688 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2689 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2690 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2691 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2692 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2693 #define RTW89_H2C_CHINFO_W1_MACID_TX BIT(29)
2696 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2700 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2717 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2721 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2722 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2723 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2724 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2726 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2731 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2734 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2738 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2741 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2743 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2762 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2763 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2777 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2778 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2781 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2782 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2783 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2787 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2790 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2813 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2816 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2822 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2826 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2827 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_TXBCN BIT(19)
2830 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2852 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2853 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2857 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2860 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2862 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2866 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2870 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2876 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
2879 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
2886 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2893 #define RTW89_H2C_MLO_LINK_CFG_W0_OPTION GENMASK(19, 16)
2912 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); in RTW89_SET_FWCMD_P2P_ACT()
2917 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); in RTW89_SET_FWCMD_P2P_TYPE()
2922 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); in RTW89_SET_FWCMD_P2P_ALL_SLEP()
2957 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); in RTW89_SET_FWCMD_TSF32_TOGL_BAND()
2962 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); in RTW89_SET_FWCMD_TSF32_TOGL_EN()
2972 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); in RTW89_SET_FWCMD_TSF32_TOGL_EARLY()
3018 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1()
3043 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); in RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL()
3048 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); in RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY()
3053 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); in RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH()
3068 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); in RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G()
3073 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); in RTW89_SET_FWCMD_ADD_MCC_PTA_EN()
3078 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); in RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS()
3093 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); in RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN()
3103 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET()
3133 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); in RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP()
3148 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16)); in RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT()
3153 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); in RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN()
3183 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); in RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS()
3193 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); in RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS()
3221 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y()
3236 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH()
3257 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET()
3286 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); in RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP()
3297 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X()
3366 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3389 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3390 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3391 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3392 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3393 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3396 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3398 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3399 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3403 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3412 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3429 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3458 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3459 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3460 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3462 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3500 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3501 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3517 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3520 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3544 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3546 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3556 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3599 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3610 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3627 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3628 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3641 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3650 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3651 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3656 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3657 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3691 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3706 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3712 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3715 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3718 #define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)
3752 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3779 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS GENMASK(19, 16)
3830 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3861 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3869 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
3877 #define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
3878 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
3884 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3885 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3886 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3891 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3943 #define RTW89_FW_ELEMENT_ALIGN 16
3962 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3978 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3979 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3980 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3981 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3982 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3983 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3984 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3988 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3989 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3992 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3993 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3994 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3995 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3996 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3999 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
4000 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4001 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4002 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4003 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4004 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4059 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
4060 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
4061 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
4062 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
4064 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
4065 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
4066 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
4067 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
4069 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
4070 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
4071 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
4072 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
4073 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
4074 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
4075 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
4076 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
4163 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4166 #define H2C_HDR_REC_ACK BIT(14)
4167 #define H2C_HDR_DONE_ACK BIT(15)
4407 #define RTW89_H2C_MCC_DIG_W0_DM_EN BIT(8)
4409 #define RTW89_H2C_MCC_DIG_W0_SET BIT(11)
4410 #define RTW89_H2C_MCC_DIG_W0_PHY0_EN BIT(12)
4411 #define RTW89_H2C_MCC_DIG_W0_PHY1_EN BIT(13)
4412 #define RTW89_H2C_MCC_DIG_W0_CENTER_CH GENMASK(23, 16)
4416 #define RTW89_H2C_MCC_DIG_W1_BMASK_LSB GENMASK(23, 16)
4641 u8 msbk_d[2][2][16];