Lines Matching +full:16 +full:bit
48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
69 #define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
78 #define FRF_AB_EE_VPD_LENGTH_LBN 16
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
150 #define FRF_AB_PCIE_RXEQCTL_L_LBN 16
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
196 #define FRF_AB_PCIE_DEQ4_LBN 16
208 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):
214 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
248 * FR_AB_HW_INIT_REG_SF(128bit):
254 * FR_AZ_HW_INIT_REG(128bit):
286 #define FRF_AB_INTA_VEC_LBN 16
302 * FR_AB_NIC_STAT_REG_SF(128bit):
308 * FR_AB_NIC_STAT_REG(128bit):
322 #define FRF_AB_ONCHIP_SRAM_LBN 16
334 * FR_AB_GLB_CTL_REG_SF(128bit):
340 * FR_AB_GLB_CTL_REG(128bit):
414 #define FRF_AB_RST_CS_LBN 16
432 * FR_AZ_IOM_IND_ADR_REG(32bit):
444 * FR_AZ_IOM_IND_DAT_REG(32bit):
454 * FR_AZ_ADR_REGION_REG(128bit):
470 * FR_AZ_INT_EN_REG_KER(128bit):
486 * FR_AZ_INT_EN_REG_CHAR(128bit):
502 * FR_AZ_INT_ADR_REG_KER(128bit):
518 * FR_AZ_INT_ADR_REG_CHAR(128bit):
534 * FR_AA_INT_ACK_KER(32bit):
544 * FR_BZ_INT_ISR0_REG(128bit):
558 * FR_AB_EE_SPI_HCMD_REG(128bit):
570 #define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16
582 * FR_CZ_USR_EV_CFG(32bit):
588 #define FRF_CZ_USREV_DIS_LBN 16
594 * FR_AB_EE_SPI_HADR_REG(128bit):
606 * FR_AB_EE_SPI_HDATA_REG(128bit):
622 * FR_AB_EE_BASE_PAGE_REG(128bit):
628 #define FRF_AB_EE_EXPROM_MASK_LBN 16
634 * FR_AB_EE_VPD_SW_CNTL_REG(128bit):
648 * FR_AB_EE_VPD_SW_DATA_REG(128bit):
658 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):
672 * FR_AB_GPIO_CTL_REG(128bit):
768 #define FRF_AB_GPIO0_OUT_LBN 16
796 * FR_AZ_FATAL_INTR_REG_KER(128bit):
860 * FR_AZ_FATAL_INTR_REG_CHAR(128bit):
924 * FR_AZ_DP_CTRL_REG(128bit):
934 * FR_AZ_MEM_STAT_REG(128bit):
962 * FR_PORT0_CS_DEBUG_REG(128bit):
995 #define FRF_AB_EV_DEBUG_ADDR_LBN 16
1007 * FR_AZ_DRIVER_REG(128bit):
1012 #define FR_AZ_DRIVER_REG_STEP 16
1019 * FR_AZ_ALTERA_BUILD_REG(128bit):
1029 * FR_AZ_CSR_SPARE_REG(128bit):
1047 * FR_BZ_DEBUG_DATA_OUT_REG(128bit):
1059 * FR_BZ_EVQ_RPTR_REGP0(32bit):
1067 * FR_AA_EVQ_RPTR_REG_KER(32bit):
1075 * FR_AZ_EVQ_RPTR_REG(32bit):
1080 #define FR_AZ_EVQ_RPTR_REG_STEP 16
1084 * FR_BB_EVQ_RPTR_REGP123(32bit):
1098 * FR_BZ_TIMER_COMMAND_REGP0(128bit):
1106 * FR_AA_TIMER_COMMAND_REG_KER(128bit):
1114 * FR_AB_TIMER_COMMAND_REGP123(128bit):
1122 * FR_AA_TIMER_COMMAND_REGP0(128bit):
1140 * FR_AZ_DRV_EV_REG(128bit):
1156 * FR_AZ_EVQ_CTL_REG(128bit):
1174 * FR_AZ_EVQ_CNT1_REG(128bit):
1196 * FR_AZ_EVQ_CNT2_REG(128bit):
1218 * FR_CZ_USR_EV_REG(32bit):
1230 * FR_AZ_BUF_TBL_CFG_REG(128bit):
1240 * FR_AZ_SRM_RX_DC_CFG_REG(128bit):
1252 * FR_AZ_SRM_TX_DC_CFG_REG(128bit):
1262 * FR_AZ_SRM_CFG_REG(128bit):
1268 * FR_AZ_SRM_CFG_REG(128bit):
1286 * FR_AZ_BUF_TBL_UPD_REG(128bit):
1302 * FR_AZ_SRM_UPD_EVQ_REG(128bit):
1312 * FR_AZ_SRAM_PARITY_REG(128bit):
1330 * FR_AZ_RX_CFG_REG(128bit):
1394 * FR_AZ_RX_FILTER_CTL_REG(128bit):
1407 #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16
1426 #define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16
1434 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):
1446 * FR_BZ_RX_DESC_UPD_REGP0(128bit):
1454 * FR_AA_RX_DESC_UPD_REG_KER(128bit):
1462 * FR_AB_RX_DESC_UPD_REGP123(128bit):
1470 * FR_AA_RX_DESC_UPD_REGP0(128bit):
1490 * FR_AZ_RX_DC_CFG_REG(128bit):
1506 * FR_AZ_RX_DC_PF_WM_REG(128bit):
1518 * FR_BZ_RX_RSS_TKEY_REG(128bit):
1536 * FR_AZ_RX_NODESC_DROP_REG(128bit):
1543 #define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16
1546 * FR_AZ_RX_SELF_RST_REG(128bit):
1554 #define FRF_AB_RX_SW_RST_REG_LBN 16
1564 * FR_AZ_RX_DEBUG_REG(128bit):
1578 * FR_AZ_RX_PUSH_DROP_REG(128bit):
1588 * FR_CZ_RX_RSS_IPV6_REG1(128bit):
1606 * FR_CZ_RX_RSS_IPV6_REG2(128bit):
1624 * FR_CZ_RX_RSS_IPV6_REG3(128bit):
1644 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):
1656 * FR_BZ_TX_DESC_UPD_REGP0(128bit):
1664 * FR_AA_TX_DESC_UPD_REG_KER(128bit):
1672 * FR_AB_TX_DESC_UPD_REGP123(128bit):
1680 * FR_AA_TX_DESC_UPD_REGP0(128bit):
1702 * FR_AZ_TX_DC_CFG_REG(128bit):
1715 * FR_AA_TX_CHKSM_CFG_REG(128bit):
1731 * FR_AZ_TX_CFG_REG(128bit):
1756 #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16
1759 #define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16
1773 * FR_AZ_TX_PUSH_DROP_REG(128bit):
1783 * FR_AZ_TX_RESERVED_REG(128bit):
1829 #define FRF_AA_TX_DMA_FF_THR_LBN 16
1853 * FR_BZ_TX_PACE_REG(128bit):
1859 * FR_AA_TX_PACE_REG(128bit):
1875 * FR_AZ_TX_PACE_DROP_QID_REG(128bit):
1882 #define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16
1885 * FR_AB_TX_VLAN_REG(128bit):
1933 #define FRF_AB_TX_VLAN1_LBN 16
1943 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):
1997 #define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16
2017 * FR_AB_TX_IPFIL_TBL(128bit):
2022 #define FR_AB_TX_IPFIL_TBL_STEP 16
2023 #define FR_AB_TX_IPFIL_TBL_ROWS 16
2035 * FR_AB_MD_TXD_REG(128bit):
2042 #define FRF_AB_MD_TXD_WIDTH 16
2045 * FR_AB_MD_RXD_REG(128bit):
2052 #define FRF_AB_MD_RXD_WIDTH 16
2055 * FR_AB_MD_CS_REG(128bit):
2085 * FR_AB_MD_PHY_ADR_REG(128bit):
2092 #define FRF_AB_MD_PHY_ADR_WIDTH 16
2095 * FR_AB_MD_ID_REG(128bit):
2107 * FR_AB_MD_STAT_REG(128bit):
2125 * FR_AB_MAC_STAT_DMA_REG(128bit):
2138 #define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16
2141 * FR_AB_MAC_CTRL_REG(128bit):
2147 #define FRF_AB_MAC_XOFF_VAL_LBN 16
2148 #define FRF_AB_MAC_XOFF_VAL_WIDTH 16
2167 * FR_BB_GEN_MODE_REG(128bit):
2183 * FR_AB_MAC_MC_HASH_REG0(128bit):
2201 * FR_AB_MAC_MC_HASH_REG1(128bit):
2219 * FR_AB_GM_CFG1_REG(32bit):
2235 #define FRF_AB_GM_RST_TX_FUNC_LBN 16
2253 * FR_AB_GM_CFG2_REG(32bit):
2277 * FR_AB_GM_IPG_REG(32bit):
2285 #define FRF_AB_GM_NONB2B_IPG2_LBN 16
2293 * FR_AB_GM_HD_REG(32bit):
2307 #define FRF_AB_GM_EXDEF_TX_EN_LBN 16
2315 * FR_AB_GM_MAX_FLEN_REG(32bit):
2322 #define FRF_AB_GM_MAX_FLEN_WIDTH 16
2325 * FR_AB_GM_TEST_REG(32bit):
2341 * FR_AB_GM_ADR1_REG(32bit):
2349 #define FRF_AB_GM_ADR_B1_LBN 16
2357 * FR_AB_GM_ADR2_REG(32bit):
2365 #define FRF_AB_GM_ADR_B5_LBN 16
2369 * FR_AB_GMF_CFG0_REG(32bit):
2383 #define FRF_AB_GMF_WTMENRPLY_LBN 16
2407 * FR_AB_GMF_CFG1_REG(32bit):
2413 #define FRF_AB_GMF_CFGFRTH_LBN 16
2416 #define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16
2419 * FR_AB_GMF_CFG2_REG(32bit):
2425 #define FRF_AB_GMF_CFGHWM_LBN 16
2431 * FR_AB_GMF_CFG3_REG(32bit):
2437 #define FRF_AB_GMF_CFGHWMFT_LBN 16
2443 * FR_AB_GMF_CFG4_REG(32bit):
2453 * FR_AB_GMF_CFG5_REG(32bit):
2473 * FR_BB_TX_SRC_MAC_TBL(128bit):
2478 #define FR_BB_TX_SRC_MAC_TBL_STEP 16
2479 #define FR_BB_TX_SRC_MAC_TBL_ROWS 16
2486 #define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16
2492 #define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16
2495 * FR_BB_TX_SRC_MAC_CTL_REG(128bit):
2501 #define FRF_BB_TX_SRC_DROP_CTR_LBN 16
2502 #define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16
2511 * FR_AB_XM_ADR_LO_REG(128bit):
2521 * FR_AB_XM_ADR_HI_REG(128bit):
2528 #define FRF_AB_XM_ADR_HI_WIDTH 16
2531 * FR_AB_XM_GLB_CFG_REG(128bit):
2539 #define FRF_AB_XM_DEBUG_MODE_LBN 16
2555 * FR_AB_XM_TX_CFG_REG(128bit):
2563 #define FRF_AB_XM_IPG_LBN 16
2581 * FR_AB_XM_RX_CFG_REG(128bit):
2611 * FR_AB_XM_MGT_INT_MASK(128bit):
2617 #define FRF_AB_XM_MSK_STA_INTR_LBN 16
2631 * FR_AB_XM_FC_REG(128bit):
2637 #define FRF_AB_XM_PAUSE_TIME_LBN 16
2638 #define FRF_AB_XM_PAUSE_TIME_WIDTH 16
2657 * FR_AB_XM_PAUSE_TIME_REG(128bit):
2663 #define FRF_AB_XM_TX_PAUSE_CNT_LBN 16
2664 #define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16
2666 #define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16
2669 * FR_AB_XM_TX_PARAM_REG(128bit):
2679 #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16
2685 * FR_AB_XM_RX_PARAM_REG(128bit):
2697 * FR_AB_XM_MGT_INT_MSK_REG(128bit):
2715 * FR_AB_XX_PWR_RST_REG(128bit):
2747 #define FRF_AB_XX_SD_RST_ACT_LBN 16
2777 * FR_AB_XX_SD_CTL_REG(128bit):
2785 #define FRF_AB_XX_TERMADJ0_LBN 16
2813 * FR_AB_XX_TXDRV_CTL_REG(128bit):
2825 #define FRF_AB_XX_DEQA_LBN 16
2837 * FR_AB_XX_PRBS_CTL_REG(128bit):
2865 #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16
2893 * FR_AB_XX_PRBS_CHK_REG(128bit):
2899 #define FRF_AB_XX_REV_LB_EN_LBN 16
2935 * FR_AB_XX_PRBS_ERR_REG(128bit):
2943 #define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16
2951 * FR_AB_XX_CORE_STAT_REG(128bit):
2987 #define FRF_AB_XX_SYNC_STAT0_LBN 16
3023 * FR_AA_RX_DESC_PTR_TBL_KER(128bit):
3028 #define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16
3031 * FR_AZ_RX_DESC_PTR_TBL(128bit):
3036 #define FR_AZ_RX_DESC_PTR_TBL_STEP 16
3078 * FR_AA_TX_DESC_PTR_TBL_KER(128bit):
3083 #define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16
3086 * FR_AZ_TX_DESC_PTR_TBL(128bit):
3091 #define FR_AZ_TX_DESC_PTR_TBL_STEP 16
3139 * FR_AA_EVQ_PTR_TBL_KER(128bit):
3144 #define FR_AA_EVQ_PTR_TBL_KER_STEP 16
3147 * FR_AZ_EVQ_PTR_TBL(128bit):
3152 #define FR_AZ_EVQ_PTR_TBL_STEP 16
3177 * FR_AA_BUF_HALF_TBL_KER(64bit):
3185 * FR_AZ_BUF_HALF_TBL(64bit):
3204 * FR_AA_BUF_FULL_TBL_KER(64bit):
3212 * FR_AZ_BUF_FULL_TBL(64bit):
3242 * FR_AZ_RX_FILTER_TBL0(128bit):
3250 * FR_AB_RX_FILTER_TBL1(128bit):
3269 #define FRF_AZ_DEST_PORT_TCP_WIDTH 16
3270 #define FRF_AZ_SRC_IP_LBN 16
3273 #define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16
3276 * FR_CZ_RX_MAC_FILTER_TBL0(128bit):
3299 #define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16
3304 * FR_AZ_TIMER_TBL(128bit):
3309 #define FR_AZ_TIMER_TBL_STEP 16
3321 #define FRF_CZ_RELOAD_TIMER_VAL_LBN 16
3341 * FR_BZ_TX_PACE_TBL(128bit):
3346 #define FR_AZ_TX_PACE_TBL_STEP 16
3350 * FR_AA_TX_PACE_TBL(128bit):
3355 /* FR_AZ_TX_PACE_TBL_STEP 16 */
3362 * FR_BZ_RX_INDIRECTION_TBL(7bit):
3367 #define FR_BZ_RX_INDIRECTION_TBL_STEP 16
3374 * FR_CZ_TX_FILTER_TBL0(128bit):
3379 #define FR_CZ_TX_FILTER_TBL0_STEP 16
3389 #define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16
3390 #define FRF_CZ_TIFT_SRC_IP_LBN 16
3393 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16
3396 * FR_CZ_TX_MAC_FILTER_TBL0(128bit):
3401 #define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16
3413 #define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16
3418 * FR_CZ_MC_TREG_SMEM(32bit):
3430 * FR_BB_MSIX_VECTOR_TABLE(128bit):
3435 #define FR_BZ_MSIX_VECTOR_TABLE_STEP 16
3438 * FR_CZ_MSIX_VECTOR_TABLE(128bit):
3443 /* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */
3458 * FR_BB_MSIX_PBA_TABLE(32bit):
3459 * MSIX Pending Bit Array
3466 * FR_CZ_MSIX_PBA_TABLE(32bit):
3467 * MSIX Pending Bit Array
3478 * FR_AZ_SRM_DBG_REG(64bit):
3496 * FR_AA_INT_ACK_CHAR(32bit):
3604 #define FSF_AZ_RX_EV_BYTE_CNT_LBN 16
3642 #define FSF_AZ_TX_EV_PORT_LBN 16