Lines Matching +full:16 +full:bit
140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
141 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
142 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
143 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
150 #define MT_PLE_HOST_RPT0_TX_LATENCY BIT(3)
175 #define MT_MDP_DCR0_DAMSDU_EN BIT(15)
176 #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19)
182 #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2)
203 #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)
212 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
217 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
224 #define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16)
229 #define MT_IFS_SIFS GENMASK(22, 16)
237 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
238 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
248 #define MT_DMA_DCR0_RXD_G5_EN BIT(23)
259 #define MT_WTBLOFF_TOP_ADM_BACKOFFTIME BIT(29)
266 #define MT_ETBF_TX_FB_CPL GENMASK(31, 16)
275 #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16)
280 #define MT_ETBF_RX_FB_HE GENMASK(23, 16)
297 #define MT_LPON_TCR_SW_WRITE BIT(0)
298 #define MT_LPON_TCR_SW_ADJUST BIT(1)
316 #define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16)
380 /* rx ampdu count, 32-bit */
383 /* rx ampdu bytes count, 32-bit */
407 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16)
414 #define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16)
429 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
434 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
449 #define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16)
468 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
469 #define MT_WTBL_UPDATE_BUSY BIT(31)
487 #define MT_AGG_PCR0_MM_PROT BIT(0)
488 #define MT_AGG_PCR0_GF_PROT BIT(1)
489 #define MT_AGG_PCR0_BW20_PROT BIT(2)
490 #define MT_AGG_PCR0_BW40_PROT BIT(4)
491 #define MT_AGG_PCR0_BW80_PROT BIT(6)
493 #define MT_AGG_PCR0_VHT_PROT BIT(13)
494 #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15)
501 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
504 #define MT_AGG_ACR_PPDU_TXS2H BIT(1)
508 #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6)
513 #define MT_AGG_ATCR_MAC_BFF_TIME_EN BIT(30)
523 #define MT_ARB_SCR_TX_DISABLE BIT(8)
524 #define MT_ARB_SCR_RX_DISABLE BIT(9)
534 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
535 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
536 #define MT_WF_RFCR_DROP_VERSION BIT(3)
537 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
538 #define MT_WF_RFCR_DROP_MCAST BIT(5)
539 #define MT_WF_RFCR_DROP_BCAST BIT(6)
540 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
541 #define MT_WF_RFCR_DROP_A3_MAC BIT(8)
542 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
543 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
544 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
545 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
546 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
547 #define MT_WF_RFCR_DROP_CTS BIT(14)
548 #define MT_WF_RFCR_DROP_RTS BIT(15)
549 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
550 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
551 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
552 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
553 #define MT_WF_RFCR_DROP_NDPA BIT(20)
554 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
557 #define MT_WF_RFCR1_DROP_ACK BIT(4)
558 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
559 #define MT_WF_RFCR1_DROP_BA BIT(6)
560 #define MT_WF_RFCR1_DROP_CFEND BIT(7)
561 #define MT_WF_RFCR1_DROP_CFACK BIT(8)
564 #define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21)
567 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
569 #define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16)
572 #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16)
585 #define MT_WFDMA0_RST_LOGIC_RST BIT(4)
586 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)
589 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
590 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)
591 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)
596 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
597 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
598 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
599 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
600 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
605 #define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10)
617 #define MT_WFDMA1_RST_LOGIC_RST BIT(4)
618 #define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5)
621 #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0)
622 #define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1)
623 #define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2)
626 #define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
627 #define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
628 #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28)
629 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27)
630 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
642 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
643 #define MT_WFDMA_HOST_CONFIG_WED BIT(1)
648 #define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16)
651 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
655 #define MT_PCIE_RECOG_ID_SEM BIT(31)
668 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
669 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
670 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
677 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
678 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
679 #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
714 #define MT_INT_RX_DONE_BAND0 BIT(16)
715 #define MT_INT_RX_DONE_BAND1 BIT(17)
716 #define MT_INT_RX_DONE_WM BIT(0)
717 #define MT_INT_RX_DONE_WA BIT(1)
718 #define MT_INT_RX_DONE_WA_MAIN BIT(1)
719 #define MT_INT_RX_DONE_WA_EXT BIT(2)
720 #define MT_INT_MCU_CMD BIT(29)
721 #define MT_INT_RX_DONE_BAND0_MT7916 BIT(22)
722 #define MT_INT_RX_DONE_BAND1_MT7916 BIT(23)
723 #define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2)
724 #define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3)
726 #define MT_INT_WED_RX_DONE_BAND0_MT7916 BIT(18)
727 #define MT_INT_WED_RX_DONE_BAND1_MT7916 BIT(19)
728 #define MT_INT_WED_RX_DONE_WA_MAIN_MT7916 BIT(1)
729 #define MT_INT_WED_RX_DONE_WA_MT7916 BIT(17)
748 #define MT_INT_TX_DONE_FWDL BIT(26)
749 #define MT_INT_TX_DONE_MCU_WM BIT(27)
750 #define MT_INT_TX_DONE_MCU_WA BIT(15)
751 #define MT_INT_TX_DONE_BAND0 BIT(30)
752 #define MT_INT_TX_DONE_BAND1 BIT(31)
753 #define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25)
754 #define MT_INT_WED_TX_DONE_BAND0 BIT(4)
755 #define MT_INT_WED_TX_DONE_BAND1 BIT(5)
762 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
763 #define MT_MCU_CMD_STOP_DMA BIT(2)
764 #define MT_MCU_CMD_RESET_DONE BIT(3)
765 #define MT_MCU_CMD_RECOVERY_DONE BIT(4)
766 #define MT_MCU_CMD_NORMAL_STATE BIT(5)
769 #define MT_MCU_CMD_WA_WDT BIT(31)
770 #define MT_MCU_CMD_WM_WDT BIT(30)
776 #define MT_TOP_PWR_KEY (0x5746 << 16)
777 #define MT_TOP_PWR_SW_RST BIT(0)
779 #define MT_TOP_PWR_HW_CTRL BIT(4)
780 #define MT_TOP_PWR_PWR_ON BIT(7)
785 #define MT_TOP_PWR_EN_MASK BIT(7)
786 #define MT_TOP_PWR_ACK_MASK BIT(6)
787 #define MT_TOP_PWR_KEY_MASK GENMASK(31, 16)
790 #define MT7986_TOP_WM_RESET_MASK BIT(0)
797 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
805 #define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16)
807 #define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16)
828 #define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0)
829 #define MT_CONN_INFRA_ADIE2_RESET_MASK BIT(2)
834 #define MT_CONN_INFRA_OSC_RC_EN_MASK BIT(7)
838 #define MT_CONN_INFRA_HW_CTRL_MASK BIT(0)
841 #define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0)
844 #define MT_CONN_INFRA_CONN_WF_MASK (BIT(29) | BIT(31))
845 #define MT_CONN_INFRA_CONN (BIT(25) | BIT(29) | BIT(31))
848 #define MT_CONN_INFRA_EMI_REQ_MASK BIT(0)
849 #define MT_CONN_INFRA_INFRA_REQ_MASK BIT(5)
861 #define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0))
862 #define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \
867 #define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16)
880 #define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0)
881 #define MT_AFE_RG_WBG_EN_BPLL_UP_MASK BIT(21)
882 #define MT_AFE_RG_WBG_EN_WPLL_UP_MASK BIT(20)
885 #define MT_AFE_RG_WBG_EN_TXCAL_WF4 BIT(29)
886 #define MT_AFE_RG_WBG_EN_TXCAL_BT BIT(21)
887 #define MT_AFE_RG_WBG_EN_TXCAL_WF3 BIT(20)
888 #define MT_AFE_RG_WBG_EN_TXCAL_WF2 BIT(19)
889 #define MT_AFE_RG_WBG_EN_TXCAL_WF1 BIT(18)
890 #define MT_AFE_RG_WBG_EN_TXCAL_WF0 BIT(17)
900 #define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16)
902 #define MT_ADIE_IDX1 GENMASK(31, 16)
918 #define MT_ADIE_EFUSE_CTRL_MASK BIT(1)
922 #define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16)
923 #define MT_ADIE_EFUSE_VALID_MASK BIT(29)
924 #define MT_ADIE_EFUSE_KICK_MASK BIT(30)
929 #define MT_ADIE_ANA_EN_MASK BIT(7)
934 #define MT_ADIE_XO_TRIM_EN_MASK BIT(7)
935 #define MT_ADIE_XTAL_DECREASE_MASK BIT(6)
957 #define MT_ADIE_7975_XTAL_EN_MASK BIT(29)
961 #define MT_ADIE_7975_XO_2_FIX_EN BIT(31)
970 #define MT_ADIE_7975_XO_CTRL6_MASK BIT(16)
977 #define MT_TOP_SPI_POLLING_BIT BIT(5)
980 #define MT_TOP_SPI_READ_ADDR_FORMAT (BIT(12) | BIT(13) | BIT(15))
981 #define MT_TOP_SPI_WRITE_ADDR_FORMAT (BIT(13) | BIT(15))
991 #define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK BIT(23)
992 #define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK BIT(29)
999 #define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0)
1016 #define MT_ADIE_TYPE_MASK BIT(1)
1072 #define MT_LED_CTRL_KICK BIT(7)
1073 #define MT_LED_CTRL_BAND BIT(4)
1074 #define MT_LED_CTRL_BLINK_MODE BIT(2)
1075 #define MT_LED_CTRL_POLARITY BIT(1)
1084 #define MT_LED_STATUS_ON GENMASK(23, 16)
1099 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
1100 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
1101 #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2)
1104 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)
1110 #define MT_TOP_WFSYS_WAKEUP_MASK BIT(0)
1122 #define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0)
1125 #define MT_TOP_WFSYS_RESET_STATUS_MASK BIT(30)
1133 #define MT_SEMA_RFSPI_STATUS_MASK BIT(1)
1141 #define MT_MCU_BUS_TIMEOUT_CG_EN_MASK BIT(28)
1142 #define MT_MCU_BUS_TIMEOUT_EN_MASK BIT(31)
1163 #define MT_SLP_WFDMA2CONN_MASK (BIT(21) | BIT(23))
1164 #define MT_SLP_CTRL_EN_MASK BIT(0)
1165 #define MT_SLP_CTRL_BSY_MASK BIT(1)
1172 #define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16)
1173 #define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3)
1174 #define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2)
1196 #define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6)
1201 #define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16))
1202 #define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16))
1208 #define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16))
1213 #define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16))
1215 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18)
1216 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29)
1218 #define MT_WF_PHY_TPC_CTRL_STAT(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 16))