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/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9211.c31 #define REG_PAGE_CONTROL 0xff
32 #define REG_CHIPID0 0x8100
33 #define REG_CHIPID0_VALUE 0x18
34 #define REG_CHIPID1 0x8101
35 #define REG_CHIPID1_VALUE 0x01
36 #define REG_CHIPID2 0x8102
37 #define REG_CHIPID2_VALUE 0xe3
39 #define REG_DSI_LANE 0xd000
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
56 regmap_reg_range(0xff, 0xff),
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Damlogic,meson8-pinctrl-cbus.yaml32 "^bank@[0-9a-f]+$":
65 reg = <0x80b0 0x28>,
66 <0x80e8 0x18>,
67 <0x8120 0x18>,
68 <0x8030 0x30>;
72 gpio-ranges = <&pinctrl_cbus 0 0 120>;
/linux/drivers/usb/cdns3/
H A Dhost.c26 #define XECP_PORT_CAP_REG 0x8000
27 #define XECP_AUX_CTRL_REG1 0x8120
56 return 0; in xhci_cdns3_resume_quirk()
124 return 0; in __cdns_host_init()
156 return 0; in cdns_host_init()
/linux/lib/
H A Dcrc-ccitt.c13 * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12.
17 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
18 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
19 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
20 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
21 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
22 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
23 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
24 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
25 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h14 #define PCI_DEVID_CN10K_RPM 0xA060
15 #define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00
16 #define PCI_DEVID_CN10KB_RPM 0xA09F
19 #define RPMX_CMRX_CFG 0x00
20 #define RPMX_CMR_GLOBAL_CFG 0x08
24 #define RPMX_CMRX_RX_ID_MAP 0x80
25 #define RPMX_CMRX_SW_INT 0x180
26 #define RPMX_CMRX_SW_INT_W1S 0x188
27 #define RPMX_CMRX_SW_INT_ENA_W1S 0x198
28 #define RPMX_CMRX_LINK_CFG 0x1070
[all …]
/linux/include/linux/mfd/mt6332/
H A Dregisters.h10 #define MT6332_HWCID 0x8000
11 #define MT6332_SWCID 0x8002
12 #define MT6332_TOP_CON 0x8004
13 #define MT6332_DDR_VREF_AP_CON 0x8006
14 #define MT6332_DDR_VREF_DQ_CON 0x8008
15 #define MT6332_DDR_VREF_CA_CON 0x800A
16 #define MT6332_TEST_OUT 0x800C
17 #define MT6332_TEST_CON0 0x800E
18 #define MT6332_TEST_CON1 0x8010
19 #define MT6332_TESTMODE_SW 0x8012
[all …]
/linux/drivers/net/ethernet/ibm/emac/
H A Dphy.c69 if (val >= 0 && (val & BMCR_RESET) == 0) in emac_mii_reset_phy()
73 if ((val & BMCR_ISOLATE) && limit > 0) in emac_mii_reset_phy()
76 return limit <= 0; in emac_mii_reset_phy()
93 if (val >= 0 && (val & BMCR_RESET) == 0) in emac_mii_reset_gpcs()
97 if ((val & BMCR_ISOLATE) && limit > 0) in emac_mii_reset_gpcs()
100 if (limit > 0 && phy->mode == PHY_INTERFACE_MODE_SGMII) { in emac_mii_reset_gpcs()
102 gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */ in emac_mii_reset_gpcs()
103 gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */ in emac_mii_reset_gpcs()
104 gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX */ in emac_mii_reset_gpcs()
107 return limit <= 0; in emac_mii_reset_gpcs()
[all …]
/linux/drivers/usb/serial/
H A Dqcserial.c21 #define QUECTEL_EC20_PID 0x9215
25 QCSERIAL_G2K = 0, /* Gobi 2000 */
40 {DEVICE_G1K(0x05c6, 0x9211)}, /* Acer Gobi QDL device */
41 {DEVICE_G1K(0x05c6, 0x9212)}, /* Acer Gobi Modem Device */
42 {DEVICE_G1K(0x03f0, 0x1f1d)}, /* HP un2400 Gobi Modem Device */
43 {DEVICE_G1K(0x03f0, 0x201d)}, /* HP un2400 Gobi QDL Device */
44 {DEVICE_G1K(0x04da, 0x250d)}, /* Panasonic Gobi Modem device */
45 {DEVICE_G1K(0x04da, 0x250c)}, /* Panasonic Gobi QDL device */
46 {DEVICE_G1K(0x413c, 0x8172)}, /* Dell Gobi Modem device */
47 {DEVICE_G1K(0x413c, 0x8171)}, /* Dell Gobi QDL device */
[all …]
/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_hw.h12 #define ENETC_DEV_ID_PF 0xe100
13 #define ENETC_DEV_ID_VF 0xef00
14 #define ENETC_DEV_ID_PTP 0xee02
17 #define ENETC_BAR_REGS 0
19 /** SI regs, offset: 0h */
20 #define ENETC_SIMR 0
22 #define ENETC_SIMR_RSSE BIT(0)
23 #define ENETC_SICTR0 0x18
24 #define ENETC_SICTR1 0x1c
25 #define ENETC_SIPCAPR0 0x20
[all …]
/linux/drivers/media/usb/gspca/
H A Dspca500.c26 #define AgfaCl20 0
55 .priv = 0},
68 .priv = 0},
87 {0x00, 0x0003, 0x816b}, /* SSI not active sync with vsync,
88 * hue (H byte) = 0,
92 {0x00, 0x0000, 0x8167}, /* brightness = 0 */
93 {0x00, 0x0020, 0x8168}, /* contrast = 0 */
94 {0x00, 0x0003, 0x816b}, /* SSI not active sync with vsync,
95 * hue (H byte) = 0, saturation/hue enable,
97 * was 0x0003, now 0x0000.
[all …]
/linux/drivers/clk/qcom/
H A Ddispcc1-sa8775p.c59 { 249600000, 2020000000, 0 },
63 .l = 0x3a,
64 .alpha = 0x9800,
65 .config_ctl_val = 0x20485699,
66 .config_ctl_hi_val = 0x00182261,
67 .config_ctl_hi1_val = 0x32aa299c,
68 .user_ctl_val = 0x00000000,
69 .user_ctl_hi_val = 0x00400805,
73 .offset = 0x0,
90 .l = 0x1f,
[all …]
H A Ddispcc0-sa8775p.c59 { 249600000, 2020000000, 0 },
63 .l = 0x3a,
64 .alpha = 0x9800,
65 .config_ctl_val = 0x20485699,
66 .config_ctl_hi_val = 0x00182261,
67 .config_ctl_hi1_val = 0x32aa299c,
68 .user_ctl_val = 0x00000000,
69 .user_ctl_hi_val = 0x00400805,
73 .offset = 0x0,
90 .l = 0x1f,
[all …]
H A Ddispcc-sm8550.c52 #define DISP_CC_MISC_CMD 0xF000
75 { 249600000, 2000000000, 0 },
79 .l = 0xd,
80 .alpha = 0x6492,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x82aa299c,
84 .test_ctl_val = 0x00000000,
85 .test_ctl_hi_val = 0x00000003,
86 .test_ctl_hi1_val = 0x00009000,
[all …]
H A Decpricc-qdu1000.c46 { 249600000, 2020000000, 0 },
51 .l = 0x24,
52 .alpha = 0x7555,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00182261,
55 .config_ctl_hi1_val = 0x32aa299c,
56 .user_ctl_val = 0x00000000,
57 .user_ctl_hi_val = 0x00000805,
61 .offset = 0x0,
66 .enable_reg = 0x0,
[all …]
/linux/drivers/media/i2c/
H A Dar0521.c31 #define AR0521_MIN_X_ADDR_START 0u
32 #define AR0521_MIN_Y_ADDR_START 0u
46 #define AR0521_ANA_GAIN_MIN 0x00
47 #define AR0521_ANA_GAIN_MAX 0x3f
48 #define AR0521_ANA_GAIN_STEP 0x01
49 #define AR0521_ANA_GAIN_DEFAULT 0x00
52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300
53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340
55 #define AR0521_REG_CHIP_ID 0x3000
56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
/linux/include/linux/
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x01060
[all...]
/linux/drivers/net/usb/
H A Dqmi_wwan.c59 QMI_WWAN_FLAG_RAWIP = 1 << 0,
65 QMI_WWAN_QUIRK_DTR = 1 << 0, /* needs "set DTR" request */
89 return 0; in qmimux_open()
95 return 0; in qmimux_stop()
106 hdr->pad = 0; in qmimux_start_xmit()
130 dev->hard_header_len = 0; in qmimux_setup()
131 dev->addr_len = 0; in qmimux_setup()
164 unsigned int len, offset = 0, pad_len, pkt_len; in qmimux_rx_fixup()
176 return 0; in qmimux_rx_fixup()
179 if (hdr->pad & 0x80) in qmimux_rx_fixup()
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_rfk.c26 static const u32 _tssi_de_cck_long[RF_PATH_NUM_8852C] = {0x5858, 0x7858};
27 static const u32 _tssi_de_cck_short[RF_PATH_NUM_8852C] = {0x5860, 0x7860};
28 static const u32 _tssi_de_mcs_20m[RF_PATH_NUM_8852C] = {0x5838, 0x7838};
29 static const u32 _tssi_de_mcs_40m[RF_PATH_NUM_8852C] = {0x5840, 0x7840};
30 static const u32 _tssi_de_mcs_80m[RF_PATH_NUM_8852C] = {0x5848, 0x7848};
31 static const u32 _tssi_de_mcs_80m_80m[RF_PATH_NUM_8852C] = {0x5850, 0x7850};
32 static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8852C] = {0x5828, 0x7828};
33 static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852C] = {0x5830, 0x7830};
36 0x8120, 0xc0d4, 0xc0d8, 0xc0e8, 0x8220, 0xc1d4, 0xc1d8, 0xc1e8
40 0xdf, 0x5f, 0x8f, 0x97, 0xa3, 0x5, 0x10005
[all …]
H A Drtw8852bt_rfk.c16 #define RTW8852BT_RXDCK_VER 0x1
17 #define RTW8852BT_IQK_VER 0x2a
20 #define RTW8852BT_DPK_VER 0x06
24 #define DPK_TXAGC_LOWER 0x2e
25 #define DPK_TXAGC_UPPER 0x3f
26 #define DPK_TXAGC_INVAL 0xff
27 #define RFREG_MASKRXBB 0x003e0
28 #define RFREG_MASKMODE 0xf0000
31 RF_SHUT_DOWN = 0x0,
32 RF_STANDBY = 0x1,
[all …]
H A Drtw8852b_rfk.c16 #define RTW8852B_RXDCK_VER 0x1
17 #define RTW8852B_IQK_VER 0x2a
22 #define RTW8852B_DPK_VER 0x0d
28 #define DPK_TXAGC_LOWER 0x2e
29 #define DPK_TXAGC_UPPER 0x3f
30 #define DPK_TXAGC_INVAL 0xff
31 #define RFREG_MASKRXBB 0x003e0
32 #define RFREG_MASKMODE 0xf0000
35 LBK_RXIQK = 0x06,
36 SYNC = 0x10,
[all …]
H A Dreg.h8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A
11 #define R_AX_SYS_ISO_CTRL 0x0000
17 #define R_AX_SYS_FUNC_EN 0x0002
19 #define B_AX_FEN_BBRSTB BIT(0)
21 #define R_AX_SYS_PW_CTRL 0x0004
36 #define R_AX_SYS_CLK_CTRL 0x0008
39 #define R_AX_SYS_SWR_CTRL1 0x0010
42 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
46 #define R_AX_RSV_CTRL 0x001C
50 #define R_AX_AFE_LDO_CTRL 0x0020
[all …]
/linux/sound/pci/
H A Dvia82xx.c52 #if 0
64 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
91 MODULE_PARM_DESC(dxs_support, "Support for DXS channels (0 = auto, 1 = enable, 2 = disable, 3 = 48k…
93 MODULE_PARM_DESC(dxs_init_volume, "initial DXS volume (0-31)");
103 #define VIA_REV_686_A 0x10
104 #define VIA_REV_686_B 0x11
105 #define VIA_REV_686_C 0x12
106 #define VIA_REV_686_D 0x13
107 #define VIA_REV_686_E 0x14
108 #define VIA_REV_686_H 0x20
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dbnx2.h30 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
40 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
57 #define RX_BD_FLAGS_NOPUSH (1<<0)
71 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
279 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
321 #define BNX2_L2CTX_TYPE 0x00000000
322 #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
323 #define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
324 #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
327 #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
[all …]

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