Lines Matching +full:0 +full:x8120
52 #define DISP_CC_MISC_CMD 0xF000
75 { 249600000, 2000000000, 0 },
79 .l = 0xd,
80 .alpha = 0x6492,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x82aa299c,
84 .test_ctl_val = 0x00000000,
85 .test_ctl_hi_val = 0x00000003,
86 .test_ctl_hi1_val = 0x00009000,
87 .test_ctl_hi2_val = 0x00000034,
88 .user_ctl_val = 0x00000000,
89 .user_ctl_hi_val = 0x00000005,
93 .offset = 0x0,
110 .l = 0x1f,
111 .alpha = 0x4000,
112 .config_ctl_val = 0x20485699,
113 .config_ctl_hi_val = 0x00182261,
114 .config_ctl_hi1_val = 0x82aa299c,
115 .test_ctl_val = 0x00000000,
116 .test_ctl_hi_val = 0x00000003,
117 .test_ctl_hi1_val = 0x00009000,
118 .test_ctl_hi2_val = 0x00000034,
119 .user_ctl_val = 0x00000000,
120 .user_ctl_hi_val = 0x00000005,
124 .offset = 0x1000,
141 { P_BI_TCXO, 0 },
153 { P_BI_TCXO, 0 },
167 { P_BI_TCXO, 0 },
183 { P_BI_TCXO, 0 },
197 { P_BI_TCXO, 0 },
215 { P_BI_TCXO, 0 },
227 { P_BI_TCXO, 0 },
239 { P_BI_TCXO, 0 },
255 { P_BI_TCXO, 0 },
269 { P_SLEEP_CLK, 0 },
277 F(19200000, P_BI_TCXO, 1, 0, 0),
278 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
279 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
284 .cmd_rcgr = 0x82e8,
285 .mnd_width = 0,
299 F(19200000, P_BI_TCXO, 1, 0, 0),
304 .cmd_rcgr = 0x8108,
305 .mnd_width = 0,
319 .cmd_rcgr = 0x8124,
320 .mnd_width = 0,
334 .cmd_rcgr = 0x81bc,
335 .mnd_width = 0,
349 .cmd_rcgr = 0x8170,
350 .mnd_width = 0,
363 .cmd_rcgr = 0x818c,
378 .cmd_rcgr = 0x81a4,
393 .cmd_rcgr = 0x8220,
394 .mnd_width = 0,
408 .cmd_rcgr = 0x8204,
409 .mnd_width = 0,
422 .cmd_rcgr = 0x81d4,
437 .cmd_rcgr = 0x81ec,
452 .cmd_rcgr = 0x8284,
453 .mnd_width = 0,
467 .cmd_rcgr = 0x8238,
468 .mnd_width = 0,
481 .cmd_rcgr = 0x8254,
496 .cmd_rcgr = 0x826c,
511 .cmd_rcgr = 0x82d0,
512 .mnd_width = 0,
526 .cmd_rcgr = 0x82b4,
527 .mnd_width = 0,
540 .cmd_rcgr = 0x829c,
555 .cmd_rcgr = 0x8140,
556 .mnd_width = 0,
570 .cmd_rcgr = 0x8158,
571 .mnd_width = 0,
585 F(19200000, P_BI_TCXO, 1, 0, 0),
586 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
587 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
588 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
589 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
590 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
591 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
592 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
593 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
598 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
599 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
600 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
605 F(19200000, P_BI_TCXO, 1, 0, 0),
606 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
607 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
608 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
609 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
610 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
611 F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
612 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
617 .cmd_rcgr = 0x80d8,
618 .mnd_width = 0,
632 .cmd_rcgr = 0x80a8,
647 .cmd_rcgr = 0x80c0,
662 .cmd_rcgr = 0x80f0,
663 .mnd_width = 0,
677 F(32000, P_SLEEP_CLK, 1, 0, 0),
682 .cmd_rcgr = 0xe05c,
683 .mnd_width = 0,
697 .cmd_rcgr = 0xe03c,
698 .mnd_width = 0,
712 .reg = 0x8120,
713 .shift = 0,
726 .reg = 0x813c,
727 .shift = 0,
740 .reg = 0x8188,
741 .shift = 0,
755 .reg = 0x821c,
756 .shift = 0,
770 .reg = 0x8250,
771 .shift = 0,
785 .reg = 0x82cc,
786 .shift = 0,
800 .halt_reg = 0xe058,
803 .enable_reg = 0xe058,
804 .enable_mask = BIT(0),
818 .halt_reg = 0xa020,
821 .enable_reg = 0xa020,
822 .enable_mask = BIT(0),
836 .halt_reg = 0x80a4,
839 .enable_reg = 0x80a4,
840 .enable_mask = BIT(0),
854 .halt_reg = 0x8028,
857 .enable_reg = 0x8028,
858 .enable_mask = BIT(0),
872 .halt_reg = 0x802c,
875 .enable_reg = 0x802c,
876 .enable_mask = BIT(0),
890 .halt_reg = 0x8030,
893 .enable_reg = 0x8030,
894 .enable_mask = BIT(0),
908 .halt_reg = 0x8034,
911 .enable_reg = 0x8034,
912 .enable_mask = BIT(0),
926 .halt_reg = 0x8058,
929 .enable_reg = 0x8058,
930 .enable_mask = BIT(0),
944 .halt_reg = 0x804c,
947 .enable_reg = 0x804c,
948 .enable_mask = BIT(0),
962 .halt_reg = 0x8040,
965 .enable_reg = 0x8040,
966 .enable_mask = BIT(0),
980 .halt_reg = 0x8048,
983 .enable_reg = 0x8048,
984 .enable_mask = BIT(0),
998 .halt_reg = 0x8050,
1001 .enable_reg = 0x8050,
1002 .enable_mask = BIT(0),
1016 .halt_reg = 0x8054,
1019 .enable_reg = 0x8054,
1020 .enable_mask = BIT(0),
1034 .halt_reg = 0x8044,
1037 .enable_reg = 0x8044,
1038 .enable_mask = BIT(0),
1052 .halt_reg = 0x8074,
1055 .enable_reg = 0x8074,
1056 .enable_mask = BIT(0),
1070 .halt_reg = 0x8070,
1073 .enable_reg = 0x8070,
1074 .enable_mask = BIT(0),
1088 .halt_reg = 0x8064,
1091 .enable_reg = 0x8064,
1092 .enable_mask = BIT(0),
1106 .halt_reg = 0x806c,
1109 .enable_reg = 0x806c,
1110 .enable_mask = BIT(0),
1124 .halt_reg = 0x805c,
1127 .enable_reg = 0x805c,
1128 .enable_mask = BIT(0),
1142 .halt_reg = 0x8060,
1145 .enable_reg = 0x8060,
1146 .enable_mask = BIT(0),
1160 .halt_reg = 0x8068,
1163 .enable_reg = 0x8068,
1164 .enable_mask = BIT(0),
1178 .halt_reg = 0x808c,
1181 .enable_reg = 0x808c,
1182 .enable_mask = BIT(0),
1196 .halt_reg = 0x8088,
1199 .enable_reg = 0x8088,
1200 .enable_mask = BIT(0),
1214 .halt_reg = 0x8080,
1217 .enable_reg = 0x8080,
1218 .enable_mask = BIT(0),
1232 .halt_reg = 0x8084,
1235 .enable_reg = 0x8084,
1236 .enable_mask = BIT(0),
1250 .halt_reg = 0x8078,
1253 .enable_reg = 0x8078,
1254 .enable_mask = BIT(0),
1268 .halt_reg = 0x807c,
1271 .enable_reg = 0x807c,
1272 .enable_mask = BIT(0),
1286 .halt_reg = 0x809c,
1289 .enable_reg = 0x809c,
1290 .enable_mask = BIT(0),
1304 .halt_reg = 0x80a0,
1307 .enable_reg = 0x80a0,
1308 .enable_mask = BIT(0),
1322 .halt_reg = 0x8094,
1325 .enable_reg = 0x8094,
1326 .enable_mask = BIT(0),
1340 .halt_reg = 0x8098,
1343 .enable_reg = 0x8098,
1344 .enable_mask = BIT(0),
1358 .halt_reg = 0x8090,
1361 .enable_reg = 0x8090,
1362 .enable_mask = BIT(0),
1376 .halt_reg = 0x8038,
1379 .enable_reg = 0x8038,
1380 .enable_mask = BIT(0),
1394 .halt_reg = 0x803c,
1397 .enable_reg = 0x803c,
1398 .enable_mask = BIT(0),
1412 .halt_reg = 0xa004,
1415 .enable_reg = 0xa004,
1416 .enable_mask = BIT(0),
1430 .halt_reg = 0x800c,
1433 .enable_reg = 0x800c,
1434 .enable_mask = BIT(0),
1448 .halt_reg = 0xa010,
1451 .enable_reg = 0xa010,
1452 .enable_mask = BIT(0),
1466 .halt_reg = 0x8018,
1469 .enable_reg = 0x8018,
1470 .enable_mask = BIT(0),
1484 .halt_reg = 0xc004,
1487 .enable_reg = 0xc004,
1488 .enable_mask = BIT(0),
1502 .halt_reg = 0x8004,
1505 .enable_reg = 0x8004,
1506 .enable_mask = BIT(0),
1520 .halt_reg = 0x8008,
1523 .enable_reg = 0x8008,
1524 .enable_mask = BIT(0),
1538 .halt_reg = 0xc00c,
1541 .enable_reg = 0xc00c,
1542 .enable_mask = BIT(0),
1556 .halt_reg = 0xc008,
1559 .enable_reg = 0xc008,
1560 .enable_mask = BIT(0),
1574 .halt_reg = 0xa01c,
1577 .enable_reg = 0xa01c,
1578 .enable_mask = BIT(0),
1592 .halt_reg = 0x8024,
1595 .enable_reg = 0x8024,
1596 .enable_mask = BIT(0),
1610 .halt_reg = 0xe074,
1613 .enable_reg = 0xe074,
1614 .enable_mask = BIT(0),
1628 .gdscr = 0x9000,
1637 .gdscr = 0xb000,
1731 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1732 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1733 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1745 .max_register = 0x11008,
1787 lucid_ole_vco[0].max_freq = 2100000000; in disp_cc_sm8550_probe()
1789 disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] = in disp_cc_sm8550_probe()
1792 disp_cc_pll0_config.l = 0x1f; in disp_cc_sm8550_probe()
1793 disp_cc_pll0_config.alpha = 0x4000; in disp_cc_sm8550_probe()
1794 disp_cc_pll0_config.user_ctl_val = 0x1; in disp_cc_sm8550_probe()
1795 disp_cc_pll1_config.user_ctl_val = 0x1; in disp_cc_sm8550_probe()
1803 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); in disp_cc_sm8550_probe()
1806 qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ in disp_cc_sm8550_probe()
1814 return 0; in disp_cc_sm8550_probe()