69 		if (val >= 0 && (val & BMCR_RESET) == 0)  in emac_mii_reset_phy()
73 	if ((val & BMCR_ISOLATE) && limit > 0)  in emac_mii_reset_phy()
76 	return limit <= 0;  in emac_mii_reset_phy()
93 		if (val >= 0 && (val & BMCR_RESET) == 0)  in emac_mii_reset_gpcs()
97 	if ((val & BMCR_ISOLATE) && limit > 0)  in emac_mii_reset_gpcs()
100 	if (limit > 0 && phy->mode == PHY_INTERFACE_MODE_SGMII) {  in emac_mii_reset_gpcs()
102 		gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */  in emac_mii_reset_gpcs()
103 		gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */  in emac_mii_reset_gpcs()
104 		gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX     */  in emac_mii_reset_gpcs()
107 	return limit <= 0;  in emac_mii_reset_gpcs()
117 	phy->pause = phy->asym_pause = 0;  in genmii_setup_aneg()
121 	if (ctl < 0)  in genmii_setup_aneg()
130 	if (adv < 0)  in genmii_setup_aneg()
151 		if (adv < 0)  in genmii_setup_aneg()
166 	return 0;  in genmii_setup_aneg()
176 	phy->pause = phy->asym_pause = 0;  in genmii_setup_forced()
179 	if (ctl < 0)  in genmii_setup_forced()
203 	return 0;  in genmii_setup_forced()
213 	if (status < 0 || (status & BMSR_LSTATUS) == 0)  in genmii_poll_link()
214 		return 0;  in genmii_poll_link()
216 		return 0;  in genmii_poll_link()
223 		int glpa = 0;  in genmii_read_link()
225 		if (lpa < 0)  in genmii_read_link()
233 			if (glpa < 0 || adv < 0)  in genmii_read_link()
241 		phy->pause = phy->asym_pause = 0;  in genmii_read_link()
255 			phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;  in genmii_read_link()
256 			phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;  in genmii_read_link()
260 		if (bmcr < 0)  in genmii_read_link()
274 		phy->pause = phy->asym_pause = 0;  in genmii_read_link()
276 	return 0;  in genmii_read_link()
288 	.phy_id		= 0x00000000,
289 	.phy_id_mask	= 0x00000000,
295 #define MII_CIS8201_10BTCSR	0x16
296 #define  TENBTCSR_ECHO_DISABLE	0x2000
297 #define MII_CIS8201_EPCR	0x17
298 #define  EPCR_MODE_MASK		0x3000
299 #define  EPCR_GMII_MODE		0x0000
300 #define  EPCR_RGMII_MODE	0x1000
301 #define  EPCR_TBI_MODE		0x2000
302 #define  EPCR_RTBI_MODE		0x3000
303 #define MII_CIS8201_ACSR	0x1c
304 #define  ACSR_PIN_PRIO_SELECT	0x0004
311 	if (epcr < 0)  in cis8201_init()
341 	return 0;  in cis8201_init()
353 	.phy_id		= 0x000fc410,
354 	.phy_id_mask	= 0x000ffff0,
361 	.phy_id		= 0x0143bc00,
362 	.phy_id_mask	= 0x0ffffff0,
370 	phy_write(phy, 0x14, 0x0ce3);  in m88e1111_init()
371 	phy_write(phy, 0x18, 0x4101);  in m88e1111_init()
372 	phy_write(phy, 0x09, 0x0e00);  in m88e1111_init()
373 	phy_write(phy, 0x04, 0x01e1);  in m88e1111_init()
374 	phy_write(phy, 0x00, 0x9140);  in m88e1111_init()
375 	phy_write(phy, 0x00, 0x1140);  in m88e1111_init()
377 	return  0;  in m88e1111_init()
393 	phy_write(phy, 0x16, 0x0002);  in m88e1112_init()
395 	phy_write(phy, 0x00, 0x0040); /* 1Gbps */  in m88e1112_init()
396 	reg_short = (u16)(phy_read(phy, 0x1a));  in m88e1112_init()
397 	reg_short |= 0x8000; /* bypass Auto-Negotiation */  in m88e1112_init()
398 	phy_write(phy, 0x1a, reg_short);  in m88e1112_init()
401 	/* Reset access to Page 0 */  in m88e1112_init()
402 	phy_write(phy, 0x16, 0x0000);  in m88e1112_init()
404 	return  0;  in m88e1112_init()
411 	reg_short = (u16)(phy_read(phy, 0x16));  in et1011c_init()
412 	reg_short &= ~(0x7);  in et1011c_init()
413 	reg_short |= 0x6;	/* RGMII Trace Delay*/  in et1011c_init()
414 	phy_write(phy, 0x16, reg_short);  in et1011c_init()
416 	reg_short = (u16)(phy_read(phy, 0x17));  in et1011c_init()
417 	reg_short &= ~(0x40);  in et1011c_init()
418 	phy_write(phy, 0x17, reg_short);  in et1011c_init()
420 	phy_write(phy, 0x1c, 0x74f0);  in et1011c_init()
421 	return 0;  in et1011c_init()
433 	.phy_id		= 0x0282f000,
434 	.phy_id_mask	= 0x0fffff00,
453 	.phy_id		= 0x01410CC0,
454 	.phy_id_mask	= 0x0ffffff0,
468 	.phy_id		= 0x01410C90,
469 	.phy_id_mask	= 0x0ffffff0,
476 	phy_write(phy, 0x1d, 0x5); /* Address debug register 5 */  in ar8035_init()
477 	phy_write(phy, 0x1e, 0x2d47); /* Value copied from u-boot */  in ar8035_init()
478 	phy_write(phy, 0x1d, 0xb);    /* Address hib ctrl */  in ar8035_init()
479 	phy_write(phy, 0x1e, 0xbc20); /* Value copied from u-boot */  in ar8035_init()
481 	return 0;  in ar8035_init()
493 	.phy_id		= 0x004dd070,
494 	.phy_id_mask	= 0xfffffff0,
517 	phy->advertising = 0;  in emac_mii_phy_probe()
521 	phy->pause = phy->asym_pause = 0;  in emac_mii_phy_probe()
529 	for (i = 0; (def = mii_phy_table[i]) != NULL; i++)  in emac_mii_phy_probe()
565 	return 0;  in emac_mii_phy_probe()