Lines Matching +full:0 +full:x8120
31 #define REG_PAGE_CONTROL 0xff
32 #define REG_CHIPID0 0x8100
33 #define REG_CHIPID0_VALUE 0x18
34 #define REG_CHIPID1 0x8101
35 #define REG_CHIPID1_VALUE 0x01
36 #define REG_CHIPID2 0x8102
37 #define REG_CHIPID2_VALUE 0xe3
39 #define REG_DSI_LANE 0xd000
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
56 regmap_reg_range(0xff, 0xff),
57 regmap_reg_range(0x8100, 0x816b),
58 regmap_reg_range(0x8200, 0x82aa),
59 regmap_reg_range(0x8500, 0x85ff),
60 regmap_reg_range(0x8600, 0x86a0),
61 regmap_reg_range(0x8700, 0x8746),
62 regmap_reg_range(0xd000, 0xd0a7),
63 regmap_reg_range(0xd400, 0xd42c),
64 regmap_reg_range(0xd800, 0xd838),
65 regmap_reg_range(0xd9c0, 0xd9d5),
75 .range_min = 0x0000,
76 .range_max = 0xda00,
78 .selector_mask = 0xff,
79 .selector_shift = 0,
80 .window_start = 0,
81 .window_len = 0x100,
93 .max_register = 0xda00,
118 if (ret < 0) {
124 if (chipid[0] != REG_CHIPID0_VALUE || chipid[1] != REG_CHIPID1_VALUE ||
126 dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n",
127 chipid[0], chipid[1], chipid[2]);
131 return 0;
137 { 0x8201, 0x18 },
138 { 0x8606, 0x61 },
139 { 0x8607, 0xa8 },
140 { 0x8714, 0x08 },
141 { 0x8715, 0x00 },
142 { 0x8718, 0x0f },
143 { 0x8722, 0x08 },
144 { 0x8723, 0x00 },
145 { 0x8726, 0x0f },
146 { 0x810b, 0xfe },
156 { 0x8202, 0x44 },
157 { 0x8204, 0xa0 },
158 { 0x8205, 0x22 },
159 { 0x8207, 0x9f },
160 { 0x8208, 0xfc },
161 /* ORR with 0xf8 here to enable DSI DN/DP swap. */
162 { 0x8209, 0x01 },
163 { 0x8217, 0x0c },
164 { 0x8633, 0x1b },
168 { 0x8120, 0x7f },
169 { 0x8120, 0xff },
173 { 0x8630, 0x85 },
174 /* 0x8588: BIT 6 set = MIPI-RX, BIT 4 unset = LVDS-TX */
175 { 0x8588, 0x40 },
176 { 0x85ff, 0xd0 },
178 { 0xd002, 0x05 },
182 { 0x810a, 0xc0 },
183 { 0x8120, 0xbf },
187 { 0x810a, 0xc1 },
188 { 0x8120, 0xff },
230 ret = regmap_write(ctx->regmap, 0x8600, 0x01);
238 ret = regmap_bulk_read(ctx->regmap, 0x8608, bc, sizeof(bc));
243 byteclk = ((bc[0] & 0xf) << 16) | (bc[1] << 8) | bc[2];
246 ret = regmap_bulk_read(ctx->regmap, 0xd082, buf, sizeof(buf));
250 width = (buf[0] << 8) | buf[1];
252 format = buf[2] & 0xf;
254 if (format == 0x3) { /* YUV422 16bit */
256 } else if (format == 0xa) { /* RGB888 24bit */
259 dev_err(ctx->dev, "Unsupported DSI pixel format 0x%01x\n",
278 dev_dbg(ctx->dev, "RX: %dx%d format=0x%01x byteclock=%d kHz\n",
281 return 0;
288 { 0xd00d, (mode->vtotal >> 8) & 0xff },
289 { 0xd00e, mode->vtotal & 0xff },
290 { 0xd00f, (mode->vdisplay >> 8) & 0xff },
291 { 0xd010, mode->vdisplay & 0xff },
292 { 0xd011, (mode->htotal >> 8) & 0xff },
293 { 0xd012, mode->htotal & 0xff },
294 { 0xd013, (mode->hdisplay >> 8) & 0xff },
295 { 0xd014, mode->hdisplay & 0xff },
296 { 0xd015, (mode->vsync_end - mode->vsync_start) & 0xff },
297 { 0xd016, (mode->hsync_end - mode->hsync_start) & 0xff },
298 { 0xd017, ((mode->vsync_start - mode->vdisplay) >> 8) & 0xff },
299 { 0xd018, (mode->vsync_start - mode->vdisplay) & 0xff },
300 { 0xd019, ((mode->hsync_start - mode->hdisplay) >> 8) & 0xff },
301 { 0xd01a, (mode->hsync_start - mode->hdisplay) & 0xff },
312 { 0xd026, 0x17 },
313 { 0xd027, 0xc3 },
314 { 0xd02d, 0x30 },
315 { 0xd031, 0x10 },
316 { 0xd023, 0x20 },
317 { 0xd038, 0x02 },
318 { 0xd039, 0x10 },
319 { 0xd03a, 0x20 },
320 { 0xd03b, 0x60 },
321 { 0xd03f, 0x04 },
322 { 0xd040, 0x08 },
323 { 0xd041, 0x10 },
324 { 0x810b, 0xee },
325 { 0x810b, 0xfe },
332 ret = regmap_write(ctx->regmap, 0x822d, 0x48);
337 ret = regmap_write(ctx->regmap, 0x8235, 0x83);
339 ret = regmap_write(ctx->regmap, 0x8235, 0x82);
341 ret = regmap_write(ctx->regmap, 0x8235, 0x81);
361 ret = regmap_read_poll_timeout(ctx->regmap, 0xd087, pval, pval & 0x8,
374 { 0x8262, 0x00 },
376 { 0x823b, 0x38 | (ctx->lvds_dual_link ? BIT(7) : 0) },
377 { 0x823e, 0x92 },
378 { 0x823f, 0x48 },
379 { 0x8240, 0x31 },
380 { 0x8243, 0x80 },
381 { 0x8244, 0x00 },
382 { 0x8245, 0x00 },
383 { 0x8249, 0x00 },
384 { 0x824a, 0x01 },
385 { 0x824e, 0x00 },
386 { 0x824f, 0x00 },
387 { 0x8250, 0x00 },
388 { 0x8253, 0x00 },
389 { 0x8254, 0x01 },
390 /* LVDS channel order, Odd:Even 0x10..A:B, 0x40..B:A */
391 { 0x8646, ctx->lvds_dual_link_even_odd_swap ? 0x40 : 0x10 },
392 { 0x8120, 0x7b },
393 { 0x816b, 0xff },
397 { 0x8559, 0x40 | (jeida ? BIT(7) : 0) |
398 (de ? BIT(5) : 0) | (bpp24 ? BIT(4) : 0) },
399 { 0x855a, 0xaa },
400 { 0x855b, 0xaa },
401 { 0x855c, ctx->lvds_dual_link ? BIT(0) : 0 },
402 { 0x85a1, 0x77 },
403 { 0x8640, 0x40 },
404 { 0x8641, 0x34 },
405 { 0x8642, 0x10 },
406 { 0x8643, 0x23 },
407 { 0x8644, 0x41 },
408 { 0x8645, 0x02 },
413 { 0x8236, 0x01 },
414 { 0x8237, ctx->lvds_dual_link ? 0x2a : 0x29 },
415 { 0x8238, 0x06 },
416 { 0x8239, 0x30 },
417 { 0x823a, 0x8e },
418 { 0x8737, 0x14 },
419 { 0x8713, 0x00 },
420 { 0x8713, 0x80 },
441 ret = regmap_read_poll_timeout(ctx->regmap, 0x871f, pval, pval & 0x80,
448 ret = regmap_read_poll_timeout(ctx->regmap, 0x8720, pval, pval & 0x80,
455 return 0;
508 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
565 gpiod_set_value(ctx->reset_gpio, 0);
601 *num_input_fmts = 0;
609 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
659 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge);
660 if (ret < 0)
670 return 0;
677 .channel = 0,
688 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
698 if (dsi_lanes < 0)
716 if (ret < 0) {
721 return 0;