Lines Matching +full:0 +full:x8120
59 { 249600000, 2020000000, 0 },
63 .l = 0x3a,
64 .alpha = 0x9800,
65 .config_ctl_val = 0x20485699,
66 .config_ctl_hi_val = 0x00182261,
67 .config_ctl_hi1_val = 0x32aa299c,
68 .user_ctl_val = 0x00000000,
69 .user_ctl_hi_val = 0x00400805,
73 .offset = 0x0,
90 .l = 0x1f,
91 .alpha = 0x4000,
92 .config_ctl_val = 0x20485699,
93 .config_ctl_hi_val = 0x00182261,
94 .config_ctl_hi1_val = 0x32aa299c,
95 .user_ctl_val = 0x00000000,
96 .user_ctl_hi_val = 0x00400805,
100 .offset = 0x1000,
117 { P_BI_TCXO, 0 },
131 { P_BI_TCXO, 0 },
147 { P_BI_TCXO, 0 },
159 { P_BI_TCXO, 0 },
171 { P_BI_TCXO, 0 },
183 { P_BI_TCXO, 0 },
195 { P_BI_TCXO, 0 },
209 { P_SLEEP_CLK, 0 },
217 F(37500000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
218 F(75000000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
223 .cmd_rcgr = 0x824c,
224 .mnd_width = 0,
238 F(19200000, P_BI_TCXO, 1, 0, 0),
243 .cmd_rcgr = 0x80ec,
244 .mnd_width = 0,
258 .cmd_rcgr = 0x8108,
259 .mnd_width = 0,
273 .cmd_rcgr = 0x81b8,
274 .mnd_width = 0,
288 .cmd_rcgr = 0x8170,
289 .mnd_width = 0,
303 .cmd_rcgr = 0x8154,
304 .mnd_width = 0,
318 .cmd_rcgr = 0x8188,
333 .cmd_rcgr = 0x81a0,
348 .cmd_rcgr = 0x826c,
363 .cmd_rcgr = 0x8284,
378 .cmd_rcgr = 0x8234,
379 .mnd_width = 0,
393 .cmd_rcgr = 0x821c,
394 .mnd_width = 0,
408 .cmd_rcgr = 0x8200,
409 .mnd_width = 0,
423 .cmd_rcgr = 0x81d0,
438 .cmd_rcgr = 0x81e8,
453 .cmd_rcgr = 0x8124,
454 .mnd_width = 0,
468 .cmd_rcgr = 0x813c,
469 .mnd_width = 0,
483 F(375000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
484 F(500000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
485 F(575000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
486 F(650000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
491 .cmd_rcgr = 0x80bc,
492 .mnd_width = 0,
506 .cmd_rcgr = 0x808c,
521 .cmd_rcgr = 0x80a4,
536 .cmd_rcgr = 0x80d4,
537 .mnd_width = 0,
551 F(32000, P_SLEEP_CLK, 1, 0, 0),
556 .cmd_rcgr = 0xc058,
557 .mnd_width = 0,
571 .cmd_rcgr = 0xc03c,
572 .mnd_width = 0,
586 .reg = 0x8104,
587 .shift = 0,
601 .reg = 0x8120,
602 .shift = 0,
616 .reg = 0x816c,
617 .shift = 0,
631 .reg = 0x8218,
632 .shift = 0,
646 .halt_reg = 0x8088,
649 .enable_reg = 0x8088,
650 .enable_mask = BIT(0),
664 .halt_reg = 0x8084,
667 .enable_reg = 0x8084,
668 .enable_mask = BIT(0),
682 .halt_reg = 0x8034,
685 .enable_reg = 0x8034,
686 .enable_mask = BIT(0),
700 .halt_reg = 0x8038,
703 .enable_reg = 0x8038,
704 .enable_mask = BIT(0),
718 .halt_reg = 0x803c,
721 .enable_reg = 0x803c,
722 .enable_mask = BIT(0),
736 .halt_reg = 0x8040,
739 .enable_reg = 0x8040,
740 .enable_mask = BIT(0),
754 .halt_reg = 0x805c,
757 .enable_reg = 0x805c,
758 .enable_mask = BIT(0),
772 .halt_reg = 0x8058,
775 .enable_reg = 0x8058,
776 .enable_mask = BIT(0),
790 .halt_reg = 0x804c,
793 .enable_reg = 0x804c,
794 .enable_mask = BIT(0),
808 .halt_reg = 0x8050,
811 .enable_reg = 0x8050,
812 .enable_mask = BIT(0),
826 .halt_reg = 0x8060,
829 .enable_reg = 0x8060,
830 .enable_mask = BIT(0),
844 .halt_reg = 0x8064,
847 .enable_reg = 0x8064,
848 .enable_mask = BIT(0),
862 .halt_reg = 0x8264,
865 .enable_reg = 0x8264,
866 .enable_mask = BIT(0),
880 .halt_reg = 0x8268,
883 .enable_reg = 0x8268,
884 .enable_mask = BIT(0),
898 .halt_reg = 0x8054,
901 .enable_reg = 0x8054,
902 .enable_mask = BIT(0),
916 .halt_reg = 0x8080,
919 .enable_reg = 0x8080,
920 .enable_mask = BIT(0),
934 .halt_reg = 0x807c,
937 .enable_reg = 0x807c,
938 .enable_mask = BIT(0),
952 .halt_reg = 0x8070,
955 .enable_reg = 0x8070,
956 .enable_mask = BIT(0),
970 .halt_reg = 0x8074,
973 .enable_reg = 0x8074,
974 .enable_mask = BIT(0),
988 .halt_reg = 0x8068,
991 .enable_reg = 0x8068,
992 .enable_mask = BIT(0),
1006 .halt_reg = 0x806c,
1009 .enable_reg = 0x806c,
1010 .enable_mask = BIT(0),
1024 .halt_reg = 0x8078,
1027 .enable_reg = 0x8078,
1028 .enable_mask = BIT(0),
1042 .halt_reg = 0x8044,
1045 .enable_reg = 0x8044,
1046 .enable_mask = BIT(0),
1060 .halt_reg = 0x8048,
1063 .enable_reg = 0x8048,
1064 .enable_mask = BIT(0),
1078 .halt_reg = 0x8014,
1081 .enable_reg = 0x8014,
1082 .enable_mask = BIT(0),
1096 .halt_reg = 0x800c,
1099 .enable_reg = 0x800c,
1100 .enable_mask = BIT(0),
1114 .halt_reg = 0x8024,
1117 .enable_reg = 0x8024,
1118 .enable_mask = BIT(0),
1132 .halt_reg = 0x801c,
1135 .enable_reg = 0x801c,
1136 .enable_mask = BIT(0),
1150 .halt_reg = 0xa004,
1153 .enable_reg = 0xa004,
1154 .enable_mask = BIT(0),
1168 .halt_reg = 0x8004,
1171 .enable_reg = 0x8004,
1172 .enable_mask = BIT(0),
1186 .halt_reg = 0x8008,
1189 .enable_reg = 0x8008,
1190 .enable_mask = BIT(0),
1204 .halt_reg = 0xe000,
1207 .enable_reg = 0xe000,
1208 .enable_mask = BIT(0),
1222 .halt_reg = 0xa00c,
1225 .enable_reg = 0xa00c,
1226 .enable_mask = BIT(0),
1240 .halt_reg = 0xa008,
1243 .enable_reg = 0xa008,
1244 .enable_mask = BIT(0),
1258 .halt_reg = 0x8030,
1261 .enable_reg = 0x8030,
1262 .enable_mask = BIT(0),
1276 .halt_reg = 0x802c,
1279 .enable_reg = 0x802c,
1280 .enable_mask = BIT(0),
1294 .halt_reg = 0x11014,
1297 .enable_reg = 0x11014,
1298 .enable_mask = BIT(0),
1307 .gdscr = 0x9000,
1308 .en_rest_wait_val = 0x2,
1309 .en_few_wait_val = 0x2,
1310 .clk_dis_wait_val = 0xf,
1319 .gdscr = 0xd000,
1320 .en_rest_wait_val = 0x2,
1321 .en_few_wait_val = 0x2,
1322 .clk_dis_wait_val = 0xf,
1409 [MDSS_DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1410 [MDSS_DISP_CC_MDSS_RSCC_BCR] = { 0xa000 },
1417 .max_register = 0x12414,
1460 qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_0_DISP_CC_SLEEP_CLK */ in disp_cc_0_sa8775p_probe()
1461 qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_0_DISP_CC_XO_CLK */ in disp_cc_0_sa8775p_probe()