Lines Matching +full:0 +full:x8120
12 #define ENETC_DEV_ID_PF 0xe100
13 #define ENETC_DEV_ID_VF 0xef00
14 #define ENETC_DEV_ID_PTP 0xee02
17 #define ENETC_BAR_REGS 0
19 /** SI regs, offset: 0h */
20 #define ENETC_SIMR 0
22 #define ENETC_SIMR_RSSE BIT(0)
23 #define ENETC_SICTR0 0x18
24 #define ENETC_SICTR1 0x1c
25 #define ENETC_SIPCAPR0 0x20
29 #define ENETC_SIPCAPR1 0x24
30 #define ENETC_SITGTGR 0x30
31 #define ENETC_SIRBGCR 0x38
33 #define ENETC_SICAR0 0x40
34 #define ENETC_SICAR1 0x44
35 #define ENETC_SICAR2 0x48
40 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
41 #define ENETC_SICAR_WR_COHERENT 0x00006727
42 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
44 #define ENETC_SIPMAR0 0x80
45 #define ENETC_SIPMAR1 0x84
46 #define ENETC_SICVLANR1 0x90
47 #define ENETC_SICVLANR2 0x94
48 #define SICVLANR_ETYPE GENMASK(15, 0)
52 /* msg size encoding: default and max msg value of 1024B encoded as 0 */
55 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0; in enetc_vsi_set_msize()
58 #define ENETC_PSIMSGRR 0x204
61 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
62 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
64 #define ENETC_VSIMSGSR 0x204 /* RO */
65 #define ENETC_VSIMSGSR_MB BIT(0)
67 #define ENETC_VSIMSGSNDAR0 0x210
68 #define ENETC_VSIMSGSNDAR1 0x214
74 #define ENETC_SIROCT 0x300
75 #define ENETC_SIRFRM 0x308
76 #define ENETC_SIRUCA 0x310
77 #define ENETC_SIRMCA 0x318
78 #define ENETC_SITOCT 0x320
79 #define ENETC_SITFRM 0x328
80 #define ENETC_SITUCA 0x330
81 #define ENETC_SITMCA 0x338
82 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
85 #define ENETC_SICBDRMR 0x800
86 #define ENETC_SICBDRSR 0x804 /* RO */
87 #define ENETC_SICBDRBAR0 0x810
88 #define ENETC_SICBDRBAR1 0x814
89 #define ENETC_SICBDRPIR 0x818
90 #define ENETC_SICBDRCIR 0x81c
91 #define ENETC_SICBDRLENR 0x820
93 #define ENETC_SICAPR0 0x900
94 #define ENETC_SICAPR1 0x904
96 #define ENETC_PSIIER 0xa00
98 #define ENETC_PSIIDR 0xa08
99 #define ENETC_SITXIDR 0xa18
100 #define ENETC_SIRXIDR 0xa28
101 #define ENETC_SIMSIVR 0xa30
103 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
104 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
106 #define ENETC_SIUEFDCR 0xe28
108 #define ENETC_SIRFSCAPR 0x1200
109 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
110 #define ENETC_SIRSSCAPR 0x1600
111 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
113 /** SI BDR sub-blocks, n = 0..7 */
115 #define ENETC_BDR_OFF(i) ((i) * 0x200)
116 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
118 #define ENETC_RBMR 0
123 #define ENETC_RBSR 0x4
124 #define ENETC_RBBSR 0x8
125 #define ENETC_RBCIR 0xc
126 #define ENETC_RBBAR0 0x10
127 #define ENETC_RBBAR1 0x14
128 #define ENETC_RBPIR 0x18
129 #define ENETC_RBLENR 0x20
130 #define ENETC_RBIER 0xa0
131 #define ENETC_RBIER_RXTIE BIT(0)
132 #define ENETC_RBIDR 0xa4
133 #define ENETC_RBICR0 0xa8
135 #define ENETC_RBICR0_ICPT_MASK 0x1ff
137 #define ENETC_RBICR1 0xac
140 #define ENETC_TBMR 0
141 #define ENETC_TBSR_BUSY BIT(0)
143 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
146 #define ENETC_TBSR 0x4
147 #define ENETC_TBBAR0 0x10
148 #define ENETC_TBBAR1 0x14
149 #define ENETC_TBPIR 0x18
150 #define ENETC_TBCIR 0x1c
151 #define ENETC_TBCIR_IDX_MASK 0xffff
152 #define ENETC_TBLENR 0x20
153 #define ENETC_TBIER 0xa0
154 #define ENETC_TBIER_TXTIE BIT(0)
155 #define ENETC_TBIDR 0xa4
156 #define ENETC_TBICR0 0xa8
158 #define ENETC_TBICR0_ICPT_MASK 0xf
160 #define ENETC_TBICR1 0xac
162 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
165 #define ENETC_PORT_BASE 0x10000
166 #define ENETC_PMR 0x0000
169 #define ENETC_PMR_PSPEED_10M 0
173 #define ENETC_PSR 0x0004 /* RO */
174 #define ENETC_PSIPMR 0x0018
177 #define ENETC_PSIPVMR 0x001c
178 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7
179 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
180 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
181 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
182 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
183 #define ENETC_PVCLCTR 0x0208
184 #define ENETC_PCVLANR1 0x0210
185 #define ENETC_PCVLANR2 0x0214
186 #define ENETC_VLAN_TYPE_C BIT(0)
188 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
189 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
192 #define ENETC_PPAUONTR 0x0410
193 #define ENETC_PPAUOFFTR 0x0414
194 #define ENETC_PTXMBAR 0x0608
195 #define ENETC_PCAPR0 0x0900
197 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
201 #define ENETC_PCAPR1 0x0904
202 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
203 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
204 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
208 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
210 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
212 #define ENETC_CBS_BW_MASK GENMASK(6, 0)
213 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
215 #define ENETC_PRSSCAPR 0x1404
216 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
217 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
218 #define ENETC_PSIVLANFMR 0x1700
219 #define ENETC_PSIVLANFMR_VS BIT(0)
220 #define ENETC_PRFSMR 0x1800
222 #define ENETC_PRFSCAPR 0x1804
223 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
224 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
225 #define ENETC_PFPMR 0x1900
227 #define ENETC_EMDIO_BASE 0x1c00
228 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
229 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
230 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
231 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
232 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
233 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
234 #define ENETC_MMCSR 0x1f00
252 #define ENETC_MMCSR_LPS BIT(0) /* Local Preemption Supported */
253 #define ENETC_MMFAECR 0x1f08
254 #define ENETC_MMFSECR 0x1f0c
255 #define ENETC_MMFAOCR 0x1f10
256 #define ENETC_MMFCRXR 0x1f14
257 #define ENETC_MMFCTXR 0x1f18
258 #define ENETC_MMHCR 0x1f1c
259 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
261 #define ENETC_PMAC_OFFSET 0x1000
263 #define ENETC_PM0_CMD_CFG 0x8008
264 #define ENETC_PM0_TX_EN BIT(0)
272 #define ENETC_PM0_MAXFRM 0x8014
274 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
275 #define ENETC_PM0_RX_FIFO 0x801c
278 #define ENETC_PM_IMDIO_BASE 0x8030
280 #define ENETC_PM0_PAUSE_QUANTA 0x8054
281 #define ENETC_PM0_PAUSE_THRESH 0x8064
283 #define ENETC_PM0_SINGLE_STEP 0x80c0
286 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
288 #define ENETC_PM0_IF_MODE 0x8300
294 #define ENETC_PM0_IFM_SSP_100 (0 << 13)
297 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0)
298 #define ENETC_PM0_IFM_IFMODE_XGMII 0
300 #define ENETC_PSIDCAPR 0x1b08
301 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0)
302 #define ENETC_PSFCAPR 0x1b18
303 #define ENETC_PSFCAPR_MSK GENMASK(15, 0)
304 #define ENETC_PSGCAPR 0x1b28
306 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0)
307 #define ENETC_PFMCAPR 0x1b38
308 #define ENETC_PFMCAPR_MSK GENMASK(15, 0)
310 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and
313 #define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac))
314 #define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac))
315 #define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac))
316 #define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac))
317 #define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac))
318 #define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac))
319 #define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac))
320 #define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac))
321 #define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac))
322 #define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac))
323 #define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac))
324 #define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac))
325 #define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac))
326 #define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac))
327 #define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac))
328 #define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac))
329 #define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac))
330 #define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac))
331 #define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac))
332 #define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac))
333 #define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac))
334 #define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac))
335 #define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac))
336 #define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac))
337 #define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac))
338 #define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac))
339 #define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac))
340 #define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac))
341 #define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac))
342 #define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac))
343 #define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac))
344 #define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac))
345 #define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac))
346 #define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac))
347 #define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac))
348 #define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac))
349 #define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac))
350 #define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac))
351 #define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac))
352 #define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac))
353 #define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac))
354 #define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac))
355 #define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac))
356 #define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac))
357 #define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac))
358 #define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac))
359 #define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac))
360 #define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac))
361 #define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac))
362 #define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac))
363 #define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac))
366 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
367 #define ENETC_PBFDSIR 0x0810
368 #define ENETC_PFDMSAPR 0x0814
369 #define ENETC_UFDMF 0x1680
370 #define ENETC_MFDMF 0x1684
371 #define ENETC_PUFDVFR 0x1780
372 #define ENETC_PMFDVFR 0x1784
373 #define ENETC_PBFDVFR 0x1788
376 #define ENETC_GLOBAL_BASE 0x20000
377 #define ENETC_G_EIPBRR0 0x0bf8
378 #define EIPBRR0_REVISION GENMASK(15, 0)
379 #define ENETC_REV_1_0 0x0100
380 #define ENETC_REV_4_1 0X0401
382 #define ENETC_G_EIPBRR1 0x0bfc
383 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
384 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
570 #define ENETC_TX_BD_L3_START GENMASK(6, 0)
573 #define ENETC_TX_BD_L3_HDR_LEN GENMASK(6, 0)
605 ENETC_TXBD_FLAGS_L4CS = BIT(0), /* For ENETC 4.1 and later */
615 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
630 memset(txbd, 0, sizeof(*txbd)); in enetc_clear_tx_bd()
634 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
665 #define ENETC_RXBD_ERR_MASK 0xff
669 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0)
676 #define ENETC_CBD_STATUS_MASK 0xf
678 #define ENETC_TPID_8021Q 0
719 #define ENETC_SI_INT_IDX 0
757 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0); in enetc_bdr_enable_rxvlan()
766 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0); in enetc_bdr_enable_txvlan()
781 BDCR_CMD_UNSPEC = 0,
796 /* class 5, command 0 */
823 /* class 7, command 0, Stream Identity Entry Configuration */
833 #define ENETC_CBDR_SID_VID_MASK 0xfff
835 #define ENETC_CBDR_SID_TG_MASK 0xc000
845 #define ENETC_CBDR_SFI_PRI_MASK 0x7
852 /* class 8, command 0, Stream Filter Instance, Short Format */
889 #define ENETC_CBDR_SGI_OIPV_MASK 0x7
899 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3
900 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc
902 /* class 9, command 0, Stream Gate Instance Table, Short Format
918 #define ENETC_CBDR_SGI_AIPV_MASK 0x7
938 #define ENETC_CBDR_SGL_IOMEN BIT(0)
941 #define ENETC_CBDR_SGL_IPV_MASK 0xe
958 #define ENETC_CBDR_FMI_MR BIT(0)
965 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
967 /* class 10: command 0/1, Flow Meter Instance Set, short Format */
1018 #define ENETC_PTCFPR(n) (0x1910 + (n) * 4) /* n = [0 ..7] */
1022 #define ENETC_PTGCR 0x11a00
1027 #define ENETC_PTGCAPR 0x11a08
1028 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0)
1031 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
1035 #define ENETC_PPSFPMR 0x11b00
1036 #define ENETC_PPSFPMR_PSFPEN BIT(0)