Lines Matching +full:0 +full:x8120
14 #define PCI_DEVID_CN10K_RPM 0xA060
15 #define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00
16 #define PCI_DEVID_CN10KB_RPM 0xA09F
19 #define RPMX_CMRX_CFG 0x00
20 #define RPMX_CMR_GLOBAL_CFG 0x08
24 #define RPMX_CMRX_RX_ID_MAP 0x80
25 #define RPMX_CMRX_SW_INT 0x180
26 #define RPMX_CMRX_SW_INT_W1S 0x188
27 #define RPMX_CMRX_SW_INT_ENA_W1S 0x198
28 #define RPMX_CMRX_LINK_CFG 0x1070
29 #define RPMX_MTI_PCS100X_CONTROL1 0x20000
31 #define RPMX_MTI_LPCSX_CONTROL(id) (0x30000 | ((id) * 0x100))
34 #define RPMX_CMRX_LINK_BASE_MASK GENMASK_ULL(11, 0)
35 #define RPMX_MTI_MAC100X_COMMAND_CONFIG 0x8010
40 #define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8
41 #define RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA 0x80B0
42 #define RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA 0x80B8
43 #define RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA 0x80C0
44 #define RPMX_MTI_MAC100X_CL01_QUANTA_THRESH 0x80C8
45 #define RPMX_MTI_MAC100X_CL23_QUANTA_THRESH 0x80D0
46 #define RPMX_MTI_MAC100X_CL45_QUANTA_THRESH 0x80D8
47 #define RPMX_MTI_MAC100X_CL67_QUANTA_THRESH 0x80E0
48 #define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108
49 #define RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA 0x8110
50 #define RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA 0x8118
51 #define RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA 0x8120
52 #define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x8128
53 #define RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH 0x8130
54 #define RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH 0x8138
55 #define RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH 0x8140
56 #define RPMX_CMR_RX_OVR_BP 0x4120
59 #define RPMX_CMR_CHAN_MSK_OR 0x4118
60 #define RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX 0x12000
61 #define RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX 0x13000
62 #define RPMX_MTI_STAT_DATA_HI_CDC 0x10038
64 #define RPM_LMAC_FWI 0xa
65 #define RPM_TX_EN BIT_ULL(0)
67 #define RPMX_CMRX_PRT_CBFC_CTL 0x5B08
70 #define RPMX_CMRX_PRT_CBFC_CTL_LOGL_EN_TX_SHIFT 0
72 #define RPMX_MTI_MAC100X_CL89_QUANTA_THRESH 0x8128
76 #define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8
77 #define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108
78 #define RPM_DEFAULT_PAUSE_TIME 0x7FF
79 #define RPMX_CMRX_RX_LOGL_XON 0x4100
81 #define RPMX_MTI_MAC100X_XIF_MODE 0x8100
84 #define RPMX_CONST1 0x2008
87 #define RPMX_MTI_STAT_STATN_CONTROL 0x10018
88 #define RPMX_MTI_STAT_DATA_HI_CDC 0x10038
92 #define RPMX_MTI_RSFEC_STAT_STATN_CONTROL 0x40018
93 #define RPMX_MTI_RSFEC_STAT_FAST_DATA_HI_CDC 0x40000
94 #define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2 0x40050
95 #define RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3 0x40058
96 #define RPMX_MTI_FCFECX_VL0_CCW_LO(a) (0x38618 + ((a) * 0x40))
97 #define RPMX_MTI_FCFECX_VL0_NCCW_LO(a) (0x38620 + ((a) * 0x40))
98 #define RPMX_MTI_FCFECX_VL1_CCW_LO(a) (0x38628 + ((a) * 0x40))
99 #define RPMX_MTI_FCFECX_VL1_NCCW_LO(a) (0x38630 + ((a) * 0x40))
100 #define RPMX_MTI_FCFECX_CW_HI(a) (0x38638 + ((a) * 0x40))
103 #define RPM2_CMRX_SW_INT 0x1b0
104 #define RPM2_CMRX_SW_INT_ENA_W1S 0x1c8
105 #define RPM2_LMAC_FWI 0x12
106 #define RPM2_CMR_CHAN_MSK_OR 0x3120
109 #define RPM2_CMR_RX_OVR_BP 0x3130
110 #define RPM2_CSR_OFFSET 0x3e00
111 #define RPM2_CMRX_PRT_CBFC_CTL 0x6510
112 #define RPM2_CMRX_RX_LMACS 0x100
113 #define RPM2_CMRX_RX_LOGL_XON 0x3100
114 #define RPM2_CMRX_RX_STAT2 0x3010
115 #define RPM2_USX_PCSX_CONTROL1 0x80000