Home
last modified time | relevance | path

Searched +full:0 +full:x2e00 (Results 1 – 25 of 32) sorted by relevance

12

/linux/drivers/char/agp/
H A Dintel-agp.h9 #define INTEL_APSIZE 0xb4
10 #define INTEL_ATTBASE 0xb8
11 #define INTEL_AGPCTRL 0xb0
12 #define INTEL_NBXCFG 0x50
13 #define INTEL_ERRSTS 0x91
16 #define I830_GMCH_CTRL 0x52
17 #define I830_GMCH_ENABLED 0x4
18 #define I830_GMCH_MEM_MASK 0x1
19 #define I830_GMCH_MEM_64M 0x1
20 #define I830_GMCH_MEM_128M 0
[all …]
/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dpearl_pcie_regs.h8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00)
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04)
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10)
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14)
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18)
13 #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c)
14 #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20)
15 #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24)
16 #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28)
17 #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c)
[all …]
/linux/sound/soc/codecs/
H A Drt5514.h15 #define RT5514_DEVICE_ID 0x10ec5514
17 #define RT5514_RESET 0x2000
18 #define RT5514_PWR_ANA1 0x2004
19 #define RT5514_PWR_ANA2 0x2008
20 #define RT5514_I2S_CTRL1 0x2010
21 #define RT5514_I2S_CTRL2 0x2014
22 #define RT5514_VAD_CTRL6 0x2030
23 #define RT5514_EXT_VAD_CTRL 0x206c
24 #define RT5514_DIG_IO_CTRL 0x2070
25 #define RT5514_PAD_CTRL1 0x2080
[all …]
/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021.dtsi23 #clock-cells = <0>;
33 ranges = <0 0x9c000000 0x400000>;
38 reg = <0x4 0x28>,
39 <0x200 0x44>,
40 <0x268 0x04>;
47 reg = <0x780 0x80>, <0xa80 0x80>;
54 reg = <0xaf00 0x34>, <0xaf80 0x58>;
62 reg = <0x14 0x3>;
65 reg = <0x18 0x2>;
68 reg = <0x34 0x6>;
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,mtu3.yaml162 port@0:
218 "^usb@[0-9a-f]+$":
252 reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
264 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
271 reg = <0x11270000 0x1000>;
288 reg = <0x112c1000 0x3000>, <0x112d0700 0x0100>;
303 reg = <0x11270000 0x1000>;
323 reg = <0x11201000 0x2e00>, <0x11203e00 0x0100>;
329 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
340 reg = <0x11200000 0x1000>;
/linux/drivers/phy/lantiq/
H A Dphy-lantiq-vrx200-pcie.c29 #define PCIE_PHY_PLL_CTRL1 0x44
31 #define PCIE_PHY_PLL_CTRL2 0x46
32 #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK GENMASK(7, 0)
36 #define PCIE_PHY_PLL_CTRL3 0x48
40 #define PCIE_PHY_PLL_CTRL4 0x4a
41 #define PCIE_PHY_PLL_CTRL5 0x4c
42 #define PCIE_PHY_PLL_CTRL6 0x4e
43 #define PCIE_PHY_PLL_CTRL7 0x50
44 #define PCIE_PHY_PLL_A_CTRL1 0x52
46 #define PCIE_PHY_PLL_A_CTRL2 0x54
[all …]
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/linux/drivers/net/wireless/intel/iwlegacy/
H A Dprph.h70 #define PRPH_BASE (0x00000)
71 #define PRPH_END (0xFFFFF)
74 #define APMG_BASE (PRPH_BASE + 0x3000)
75 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
76 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
77 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
78 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
79 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
80 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
81 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
[all …]
/linux/drivers/media/dvb-frontends/
H A Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
H A Dstv0900_sw.c43 if (max_carrier > 0x4000) in stv0900_check_signal_presence()
44 max_carrier = 0x4000; in stv0900_check_signal_presence()
46 if ((agc2_integr > 0x2000) in stv0900_check_signal_presence()
71 if (max_carrier > 0x4000) in stv0900_get_sw_loop_params()
72 max_carrier = 0x4000; in stv0900_get_sw_loop_params()
97 if ((freq_inc > max_carrier) || (freq_inc < 0)) in stv0900_get_sw_loop_params()
102 if (srate > 0) in stv0900_get_sw_loop_params()
105 if ((timeout > 100) || (timeout < 0)) in stv0900_get_sw_loop_params()
110 if ((max_steps > 100) || (max_steps < 0)) { in stv0900_get_sw_loop_params()
137 if (max_carrier > 0x4000) in stv0900_search_carr_sw_loop()
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt61pci.h20 #define RT2561s_PCI_ID 0x0301
21 #define RT2561_PCI_ID 0x0302
22 #define RT2661_PCI_ID 0x0401
27 #define RF5225 0x0001
28 #define RF5325 0x0002
29 #define RF2527 0x0003
30 #define RF2529 0x0004
41 #define CSR_REG_BASE 0x3000
42 #define CSR_REG_SIZE 0x04b0
43 #define EEPROM_BASE 0x0000
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/sound/pci/cs46xx/
H A Ddsp_spos_scb_lib.c35 if (snd_BUG_ON(ins->symbol_table.nsymbols <= 0)) in remove_symbol()
37 if (snd_BUG_ON(symbol_index < 0 || in remove_symbol()
69 for (col = 0,j = 0;j < 0x10; j++,col++) { in cs46xx_dsp_proc_scb_info_read()
72 col = 0; in cs46xx_dsp_proc_scb_info_read()
153 for (i = 0; i < dword_count ; ++i ) { in _dsp_clear_sample_buffer()
154 writel(0, dst); in _dsp_clear_sample_buffer()
164 if (snd_BUG_ON(scb->index < 0 || in cs46xx_dsp_remove_scb()
169 #if 0 in cs46xx_dsp_remove_scb()
269 (ins->the_null_scb->address << 0x10) | ins->the_null_scb->address; in _dsp_create_generic_scb()
271 scb_data[SCBfuncEntryPtr] &= 0xFFFF0000; in _dsp_create_generic_scb()
[all …]
/linux/drivers/iommu/intel/
H A Diommu.c40 #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
42 #define IOAPIC_RANGE_START (0xfee00000)
43 #define IOAPIC_RANGE_END (0xfeefffff)
44 #define IOVA_START_ADDR (0x1000)
59 static int force_on = 0;
72 return 0; in root_entry_lctp()
84 return 0; in root_entry_uctp()
101 return 0; in device_rid_cmp_key()
151 return 0; in device_rbtree_insert()
202 int intel_iommu_enabled = 0;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
H A Dgfx_7_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
H A Dgfx_8_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
H A Dgfx_8_1_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
/linux/sound/firewire/
H A Damdtp-stream.c29 #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */
33 #define TAG_NO_CIP_HEADER 0
40 #define CIP_EOH_MASK 0x80000000
42 #define CIP_SID_MASK 0x3f000000
43 #define CIP_DBS_MASK 0x00ff0000
45 #define CIP_SPH_MASK 0x00000400
47 #define CIP_DBC_MASK 0x000000ff
49 #define CIP_FMT_MASK 0x3f000000
50 #define CIP_FDF_MASK 0x00ff0000
52 #define CIP_FDF_NO_DATA 0xff
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-msm8660.c27 .l_reg = 0x3144,
28 .m_reg = 0x3148,
29 .n_reg = 0x314c,
30 .config_reg = 0x3154,
31 .mode_reg = 0x3140,
32 .status_reg = 0x3158,
45 .enable_reg = 0x34c0,
64 { P_PXO, 0 },
74 { P_PXO, 0 },
104 .ns_reg = 0x29d4,
[all …]
H A Dgcc-ipq806x.c33 .l_reg = 0x30c4,
34 .m_reg = 0x30c8,
35 .n_reg = 0x30cc,
36 .config_reg = 0x30d4,
37 .mode_reg = 0x30c0,
38 .status_reg = 0x30d8,
49 .enable_reg = 0x34c0,
50 .enable_mask = BIT(0),
62 .l_reg = 0x3164,
63 .m_reg = 0x3168,
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dpolaris10_smumgr.c55 #define POLARIS10_SMC_SIZE 0x20000
58 #define MC_CG_ARB_FREQ_F1 0x0b
63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
65 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
83 …0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000…
84 …0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000…
85 …0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000…
86 …0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000…
87 …0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100…
[all …]

12