29 #define PCIE_PHY_PLL_CTRL1				0x44
31 #define PCIE_PHY_PLL_CTRL2				0x46
32 #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK		GENMASK(7, 0)
36 #define PCIE_PHY_PLL_CTRL3				0x48
40 #define PCIE_PHY_PLL_CTRL4				0x4a
41 #define PCIE_PHY_PLL_CTRL5				0x4c
42 #define PCIE_PHY_PLL_CTRL6				0x4e
43 #define PCIE_PHY_PLL_CTRL7				0x50
44 #define PCIE_PHY_PLL_A_CTRL1				0x52
46 #define PCIE_PHY_PLL_A_CTRL2				0x54
49 #define PCIE_PHY_PLL_A_CTRL3				0x56
52 #define PCIE_PHY_PLL_STATUS				0x58
54 #define PCIE_PHY_TX1_CTRL1				0x60
58 #define PCIE_PHY_TX1_CTRL2				0x62
59 #define PCIE_PHY_TX1_CTRL3				0x64
60 #define PCIE_PHY_TX1_A_CTRL1				0x66
61 #define PCIE_PHY_TX1_A_CTRL2				0x68
62 #define PCIE_PHY_TX1_MOD1				0x6a
63 #define PCIE_PHY_TX1_MOD2				0x6c
64 #define PCIE_PHY_TX1_MOD3				0x6e
66 #define PCIE_PHY_TX2_CTRL1				0x70
69 #define PCIE_PHY_TX2_CTRL2				0x72
70 #define PCIE_PHY_TX2_A_CTRL1				0x76
71 #define PCIE_PHY_TX2_A_CTRL2				0x78
72 #define PCIE_PHY_TX2_MOD1				0x7a
73 #define PCIE_PHY_TX2_MOD2				0x7c
74 #define PCIE_PHY_TX2_MOD3				0x7e
76 #define PCIE_PHY_RX1_CTRL1				0xa0
79 #define PCIE_PHY_RX1_CTRL2				0xa2
80 #define PCIE_PHY_RX1_CDR				0xa4
81 #define PCIE_PHY_RX1_EI					0xa6
82 #define PCIE_PHY_RX1_A_CTRL				0xaa
103 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);  in ltq_vrx200_pcie_phy_common_setup()
106 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);  in ltq_vrx200_pcie_phy_common_setup()
107 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);  in ltq_vrx200_pcie_phy_common_setup()
110 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);  in ltq_vrx200_pcie_phy_common_setup()
111 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);  in ltq_vrx200_pcie_phy_common_setup()
118 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);  in ltq_vrx200_pcie_phy_common_setup()
121 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);  in ltq_vrx200_pcie_phy_common_setup()
124 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);  in ltq_vrx200_pcie_phy_common_setup()
127 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,  in ltq_vrx200_pcie_phy_common_setup()
128 			   0x4700);  in ltq_vrx200_pcie_phy_common_setup()
131 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);  in ltq_vrx200_pcie_phy_common_setup()
134 	regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);  in ltq_vrx200_pcie_phy_common_setup()
135 	regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);  in ltq_vrx200_pcie_phy_common_setup()
138 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);  in ltq_vrx200_pcie_phy_common_setup()
146 			   PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN, 0x0000);  in pcie_phy_36mhz_mode_setup()
149 			   PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK, 0x0000);  in pcie_phy_36mhz_mode_setup()
161 			   FIELD_PREP(PCIE_PHY_PLL_A_CTRL3_MMD_MASK, 0x1));  in pcie_phy_36mhz_mode_setup()
164 			   PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN, 0x0000);  in pcie_phy_36mhz_mode_setup()
167 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);  in pcie_phy_36mhz_mode_setup()
172 				      0xee));  in pcie_phy_36mhz_mode_setup()
175 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002);  in pcie_phy_36mhz_mode_setup()
176 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04);  in pcie_phy_36mhz_mode_setup()
177 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3);  in pcie_phy_36mhz_mode_setup()
178 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72);  in pcie_phy_36mhz_mode_setup()
188 				       tmp, ((tmp & 0x0070) == 0x0070), 10,  in ltq_vrx200_pcie_phy_wait_for_pll()
191 		dev_err(priv->dev, "PLL Link timeout, PLL status = 0x%04x\n",  in ltq_vrx200_pcie_phy_wait_for_pll()
196 	return 0;  in ltq_vrx200_pcie_phy_wait_for_pll()
218 	for (i = 0; i < ARRAY_SIZE(slices); i++) {  in ltq_vrx200_pcie_phy_apply_workarounds()
227 				   slices[i].def, 0x0);  in ltq_vrx200_pcie_phy_apply_workarounds()
230 	for (i = 0; i < 5; i++) {  in ltq_vrx200_pcie_phy_apply_workarounds()
232 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe);  in ltq_vrx200_pcie_phy_apply_workarounds()
233 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe);  in ltq_vrx200_pcie_phy_apply_workarounds()
234 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601);  in ltq_vrx200_pcie_phy_apply_workarounds()
236 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001);  in ltq_vrx200_pcie_phy_apply_workarounds()
239 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe);  in ltq_vrx200_pcie_phy_apply_workarounds()
240 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe);  in ltq_vrx200_pcie_phy_apply_workarounds()
241 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601);  in ltq_vrx200_pcie_phy_apply_workarounds()
243 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001);  in ltq_vrx200_pcie_phy_apply_workarounds()
260 				   priv->rcu_ahb_endian_big_endian_mask, 0x0);  in ltq_vrx200_pcie_phy_init()
281 	return 0;  in ltq_vrx200_pcie_phy_init()
302 	return 0;  in ltq_vrx200_pcie_phy_exit()
332 	return 0;  in ltq_vrx200_pcie_phy_power_on()
349 	return 0;  in ltq_vrx200_pcie_phy_power_off()
371 	mode = args->args[0];  in ltq_vrx200_pcie_phy_xlate()
412 	base = devm_platform_ioremap_resource(pdev, 0);  in ltq_vrx200_pcie_phy_probe()