Lines Matching +full:0 +full:x2e00
70 #define PRPH_BASE (0x00000)
71 #define PRPH_END (0xFFFFF)
74 #define APMG_BASE (PRPH_BASE + 0x3000)
75 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
76 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
77 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
78 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
79 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
80 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
81 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
82 #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
83 #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
84 #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
86 #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
87 #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
88 #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
90 #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
91 #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
92 #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
93 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
94 #define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */
95 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
96 #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
97 #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
99 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
141 * BSM_WR_MEM_SRC_REG = 0
149 * Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0
155 * CSR_RESET = 0
205 #define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */
206 #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup */
207 #define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */
210 #define BSM_BASE (PRPH_BASE + 0x3400)
211 #define BSM_END (PRPH_BASE + 0x3800)
213 #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */
214 #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */
215 #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */
216 #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */
217 #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */
221 * NOTE: 3945 pointers use bits 31:0 of DRAM address.
224 #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090)
225 #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094)
226 #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098)
227 #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C)
233 #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
237 #define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
238 #define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
239 #define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
240 #define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010)
241 #define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014)
242 #define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020)
243 #define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
244 #define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
259 * 0 -- EDCA BK (background) frames, lowest priority
269 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
271 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
328 #define IL49_SCD_START_OFFSET 0xa02c00
334 #define IL49_SCD_SRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x0)
341 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
342 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
345 #define IL49_SCD_EMPTY_BITS (IL49_SCD_START_OFFSET + 0x4)
350 * This register points to BC CB for queue 0, must be on 1024-byte boundary.
353 * (Index into a queue's BC CB) = (idx into queue's TFD CB) = (SSN & 0xff).
357 #define IL49_SCD_DRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x10)
362 * Set this to 0xff to enable all 8 channels (normal usage).
364 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7
366 #define IL49_SCD_TXFACT (IL49_SCD_START_OFFSET + 0x1c)
371 * Start Sequence Number; idx = (SSN & 0xff)
374 #define IL49_SCD_QUEUE_WRPTR(x) (IL49_SCD_START_OFFSET + 0x24 + (x) * 4)
382 #define IL49_SCD_QUEUE_RDPTR(x) (IL49_SCD_START_OFFSET + 0x64 + (x) * 4)
385 * Select which queues work in chain mode (1) vs. not (0).
389 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
393 #define IL49_SCD_QUEUECHAIN_SEL (IL49_SCD_START_OFFSET + 0xd0)
400 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
404 #define IL49_SCD_INTERRUPT_MASK (IL49_SCD_START_OFFSET + 0xe4)
410 * 19-10: Write mask/enable bits for bits 0-9
411 * 9: Driver should init to "0"
412 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
413 * Driver should init to "1" for aggregation mode, or "0" otherwise.
414 * 7-6: Driver should init to "0"
417 * this bit to "1" for aggregation mode, or "0" for non-agg.
418 * 4-1: Tx FIFO to use (range 0-7).
419 * 0: Queue is active (1), not active (0).
420 * Other bits should be written as "0"
426 (IL49_SCD_START_OFFSET + 0x104 + (x) * 4)
429 #define IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
436 #define IL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
457 * Driver should clear this entire area (size 0x80) to 0 after receiving
462 * 0-06: Max Tx win size for Scheduler-ACK. Driver should init to 64.
465 * 16-22: Frame limit. Driver should init to 10 (0xa).
467 * Driver should init all other bits to 0.
472 #define IL49_SCD_CONTEXT_DATA_OFFSET 0x380
476 #define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
477 #define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
479 #define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
484 * Driver should clear this entire area (size 0x100) to 0 after receiving
488 #define IL49_SCD_TX_STTS_BITMAP_OFFSET 0x400
501 * 15-9: Reserved, set to 0
503 * 3-0: Traffic ID (tid), range 0-15
505 * Driver should clear this entire area (size 32 bytes) to 0 after receiving
510 #define IL49_SCD_TRANSLATE_TBL_OFFSET 0x500
514 ((IL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
516 #define IL_SCD_TXFIFO_POS_TID (0)
518 #define IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)