Lines Matching +full:0 +full:x2e00
9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x0080
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_COEXCFG3 0x004c
40 #define MT_LDO_CTRL_0 0x006c
41 #define MT_LDO_CTRL_1 0x0070
59 #define MT_CSR_EE_CFG1 0x0104
61 #define MT_XO_CTRL0 0x0100
62 #define MT_XO_CTRL1 0x0104
63 #define MT_XO_CTRL2 0x0108
64 #define MT_XO_CTRL3 0x010c
65 #define MT_XO_CTRL4 0x0110
67 #define MT_XO_CTRL5 0x0114
70 #define MT_XO_CTRL6 0x0118
73 #define MT_XO_CTRL7 0x011c
75 #define MT_IOCFG_6 0x0124
77 #define MT_USB_U3DMA_CFG 0x9018
78 #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
92 #define MT_WLAN_MTC_CTRL 0x10148
93 #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0)
106 #define MT_INT_SOURCE_CSR 0x0200
107 #define MT_INT_MASK_CSR 0x0204
110 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
125 #define MT_WPDMA_GLO_CFG 0x0208
126 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
137 #define MT_WPDMA_RST_IDX 0x020c
139 #define MT_WPDMA_DELAY_INT_CFG 0x0210
141 #define MT_WMM_AIFSN 0x0214
142 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
145 #define MT_WMM_CWMIN 0x0218
146 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
149 #define MT_WMM_CWMAX 0x021c
150 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
153 #define MT_WMM_TXOP_BASE 0x0220
156 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
158 #define MT_WMM_CTRL 0x0230 /* MT76x0 */
159 #define MT_FCE_DMA_ADDR 0x0230
160 #define MT_FCE_DMA_LEN 0x0234
161 #define MT_USB_DMA_CFG 0x0238
163 #define MT_TSO_CTRL 0x0250
164 #define MT_HEADER_TRANS_CTRL_REG 0x0260
166 #define MT_US_CYC_CFG 0x02a4
167 #define MT_US_CYC_CNT GENMASK(7, 0)
169 #define MT_TX_RING_BASE 0x0300
170 #define MT_RX_RING_BASE 0x03c0
175 #define MT_PBF_SYS_CTRL 0x0400
176 #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)
182 #define MT_PBF_CFG 0x0404
183 #define MT_PBF_CFG_TX0Q_EN BIT(0)
190 #define MT_PBF_TX_MAX_PCNT 0x0408
191 #define MT_PBF_RX_MAX_PCNT 0x040c
193 #define MT_BCN_OFFSET_BASE 0x041c
196 #define MT_RXQ_STA 0x0430
197 #define MT_TXQ_STA 0x0434
198 #define MT_RF_CSR_CFG 0x0500
199 #define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
205 #define MT_RF_BYPASS_0 0x0504
206 #define MT_RF_BYPASS_1 0x0508
207 #define MT_RF_SETTING_0 0x050c
209 #define MT_RF_MISC 0x0518
210 #define MT_RF_DATA_WRITE 0x0524
212 #define MT_RF_CTRL 0x0528
213 #define MT_RF_CTRL_ADDR GENMASK(11, 0)
218 #define MT_RF_DATA_READ 0x052c
220 #define MT_COM_REG0 0x0730
221 #define MT_COM_REG1 0x0734
222 #define MT_COM_REG2 0x0738
223 #define MT_COM_REG3 0x073C
225 #define MT_LED_CTRL 0x0770
226 #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))
231 #define MT_LED_TX_BLINK_0 0x0774
232 #define MT_LED_TX_BLINK_1 0x0778
234 #define MT_LED_S0_BASE 0x077C
236 #define MT_LED_S1_BASE 0x0780
242 #define MT_FCE_PSE_CTRL 0x0800
243 #define MT_FCE_PARAMETERS 0x0804
244 #define MT_FCE_CSO 0x0808
246 #define MT_FCE_L2_STUFF 0x080c
247 #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0)
257 #define MT_FCE_WLAN_FLOW_CONTROL1 0x0824
259 #define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0
260 #define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4
261 #define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8
262 #define MT_FCE_PDMA_GLOBAL_CONF 0x09c4
263 #define MT_FCE_SKIP_FS 0x0a6c
265 #define MT_PAUSE_ENABLE_CONTROL1 0x0a38
267 #define MT_MAC_CSR0 0x1000
269 #define MT_MAC_SYS_CTRL 0x1004
270 #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0)
275 #define MT_MAC_ADDR_DW0 0x1008
276 #define MT_MAC_ADDR_DW1 0x100c
279 #define MT_MAC_BSSID_DW0 0x1010
280 #define MT_MAC_BSSID_DW1 0x1014
281 #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
289 #define MT_MAX_LEN_CFG 0x1018
292 #define MT_LED_CFG 0x102c
294 #define MT_AMPDU_MAX_LEN_20M1S 0x1030
295 #define MT_AMPDU_MAX_LEN_20M2S 0x1034
296 #define MT_AMPDU_MAX_LEN_40M1S 0x1038
297 #define MT_AMPDU_MAX_LEN_40M2S 0x103c
298 #define MT_AMPDU_MAX_LEN 0x1040
300 #define MT_WCID_DROP_BASE 0x106c
304 #define MT_BCN_BYPASS_MASK 0x108c
306 #define MT_MAC_APC_BSSID_BASE 0x1090
309 #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
312 #define MT_XIFS_TIME_CFG 0x1100
313 #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
319 #define MT_BKOFF_SLOT_CFG 0x1104
320 #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
323 #define MT_CH_TIME_CFG 0x110c
324 #define MT_CH_TIME_CFG_TIMER_EN BIT(0)
334 #define MT_PBF_LIFE_TIMER 0x1110
336 #define MT_BEACON_TIME_CFG 0x1114
337 #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
344 #define MT_TBTT_SYNC_CFG 0x1118
345 #define MT_TSF_TIMER_DW0 0x111c
346 #define MT_TSF_TIMER_DW1 0x1120
347 #define MT_TBTT_TIMER 0x1124
348 #define MT_TBTT_TIMER_VAL GENMASK(16, 0)
350 #define MT_INT_TIMER_CFG 0x1128
351 #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
354 #define MT_INT_TIMER_EN 0x112c
355 #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0)
358 #define MT_CH_IDLE 0x1130
359 #define MT_CH_BUSY 0x1134
360 #define MT_EXT_CH_BUSY 0x1138
361 #define MT_ED_CCA_TIMER 0x1140
363 #define MT_MAC_STATUS 0x1200
364 #define MT_MAC_STATUS_TX BIT(0)
367 #define MT_PWR_PIN_CFG 0x1204
368 #define MT_AUX_CLK_CFG 0x120c
370 #define MT_BB_PA_MODE_CFG0 0x1214
371 #define MT_BB_PA_MODE_CFG1 0x1218
372 #define MT_RF_PA_MODE_CFG0 0x121c
373 #define MT_RF_PA_MODE_CFG1 0x1220
375 #define MT_RF_PA_MODE_ADJ0 0x1228
376 #define MT_RF_PA_MODE_ADJ1 0x122c
378 #define MT_DACCLK_EN_DLY_CFG 0x1264
380 #define MT_EDCA_CFG_BASE 0x1300
382 #define MT_EDCA_CFG_TXOP GENMASK(7, 0)
387 #define MT_TX_PWR_CFG_0 0x1314
388 #define MT_TX_PWR_CFG_1 0x1318
389 #define MT_TX_PWR_CFG_2 0x131c
390 #define MT_TX_PWR_CFG_3 0x1320
391 #define MT_TX_PWR_CFG_4 0x1324
392 #define MT_TX_PIN_CFG 0x1328
393 #define MT_TX_PIN_CFG_TXANT GENMASK(3, 0)
398 #define MT_TX_BAND_CFG 0x132c
399 #define MT_TX_BAND_CFG_UPPER_40M BIT(0)
403 #define MT_HT_FBK_TO_LEGACY 0x1384
404 #define MT_TX_MPDU_ADJ_INT 0x1388
406 #define MT_TX_PWR_CFG_7 0x13d4
407 #define MT_TX_PWR_CFG_8 0x13d8
408 #define MT_TX_PWR_CFG_9 0x13dc
410 #define MT_TX_SW_CFG0 0x1330
411 #define MT_TX_SW_CFG1 0x1334
412 #define MT_TX_SW_CFG2 0x1338
414 #define MT_TXOP_CTRL_CFG 0x1340
415 #define MT_TXOP_TRUN_EN GENMASK(5, 0)
419 #define MT_TX_RTS_CFG 0x1344
420 #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
424 #define MT_TX_TIMEOUT_CFG 0x1348
427 #define MT_TX_RETRY_CFG 0x134c
428 #define MT_TX_LINK_CFG 0x1350
430 #define MT_VHT_HT_FBK_CFG0 0x1354
431 #define MT_VHT_HT_FBK_CFG1 0x1358
432 #define MT_LG_FBK_CFG0 0x135c
433 #define MT_LG_FBK_CFG1 0x1360
435 #define MT_PROT_CFG_RATE GENMASK(15, 0)
441 #define MT_CCK_PROT_CFG 0x1364
442 #define MT_OFDM_PROT_CFG 0x1368
443 #define MT_MM20_PROT_CFG 0x136c
444 #define MT_MM40_PROT_CFG 0x1370
445 #define MT_GF20_PROT_CFG 0x1374
446 #define MT_GF40_PROT_CFG 0x1378
448 #define MT_PROT_RATE GENMASK(15, 0)
460 #define MT_PROT_RATE_CCK_11 0x0003
461 #define MT_PROT_RATE_OFDM_6 0x2000
462 #define MT_PROT_RATE_OFDM_24 0x2004
463 #define MT_PROT_RATE_DUP_OFDM_24 0x2084
464 #define MT_PROT_RATE_SGI_OFDM_24 0x2104
470 #define MT_EXP_ACK_TIME 0x1380
472 #define MT_TX_PWR_CFG_0_EXT 0x1390
473 #define MT_TX_PWR_CFG_1_EXT 0x1394
475 #define MT_TX_FBK_LIMIT 0x1398
476 #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
482 #define MT_TX0_RF_GAIN_CORR 0x13a0
483 #define MT_TX1_RF_GAIN_CORR 0x13a4
484 #define MT_TX0_RF_GAIN_ATTEN 0x13a8
485 #define MT_TX0_RF_GAIN_ATTEN 0x13a8 /* MT76x0 */
487 #define MT_TX_ALC_CFG_0 0x13b0
488 #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
493 #define MT_TX_ALC_CFG_1 0x13b4
494 #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)
496 #define MT_TX_ALC_CFG_2 0x13a8
497 #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)
499 #define MT_TX_ALC_CFG_3 0x13ac
500 #define MT_TX_ALC_CFG_4 0x13c0
502 #define MT_TX0_BB_GAIN_ATTEN 0x13c0 /* MT76x0 */
504 #define MT_TX_ALC_VGA3 0x13c8
506 #define MT_TX_PROT_CFG6 0x13e0
507 #define MT_TX_PROT_CFG7 0x13e4
508 #define MT_TX_PROT_CFG8 0x13e8
510 #define MT_PIFS_TX_CFG 0x13ec
512 #define MT_RX_FILTR_CFG 0x1400
514 #define MT_RX_FILTR_CFG_CRC_ERR BIT(0)
532 #define MT_AUTO_RSP_CFG 0x1404
533 #define MT_AUTO_RSP_EN BIT(0)
535 #define MT_LEGACY_BASIC_RATE 0x1408
536 #define MT_HT_BASIC_RATE 0x140c
538 #define MT_HT_CTRL_CFG 0x1410
539 #define MT_RX_PARSER_CFG 0x1418
540 #define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0)
542 #define MT_EXT_CCA_CFG 0x141c
543 #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
550 #define MT_TX_SW_CFG3 0x1478
552 #define MT_PN_PAD_MODE 0x150c
554 #define MT_TXOP_HLDR_ET 0x1608
557 #define MT_PROT_AUTO_TX_CFG 0x1648
561 #define MT_RX_STAT_0 0x1700
562 #define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0)
565 #define MT_RX_STAT_1 0x1704
566 #define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0)
569 #define MT_RX_STAT_2 0x1708
570 #define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0)
573 #define MT_TX_STA_0 0x170c
576 #define MT_TX_STA_1 0x1710
577 #define MT_TX_STA_2 0x1714
579 #define MT_TX_STAT_FIFO 0x1718
580 #define MT_TX_STAT_FIFO_VALID BIT(0)
587 #define MT_TX_AGG_STAT 0x171c
589 #define MT_TX_AGG_CNT_BASE0 0x1720
590 #define MT_MPDU_DENSITY_CNT 0x1740
591 #define MT_TX_AGG_CNT_BASE1 0x174c
597 #define MT_TX_STAT_FIFO_EXT 0x1798
598 #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
601 #define MT_WCID_TX_RATE_BASE 0x1c00
604 #define MT_BBP_CORE_BASE 0x2000
605 #define MT_BBP_IBI_BASE 0x2100
606 #define MT_BBP_AGC_BASE 0x2300
607 #define MT_BBP_TXC_BASE 0x2400
608 #define MT_BBP_RXC_BASE 0x2500
609 #define MT_BBP_TXO_BASE 0x2600
610 #define MT_BBP_TXBE_BASE 0x2700
611 #define MT_BBP_RXFE_BASE 0x2800
612 #define MT_BBP_RXO_BASE 0x2900
613 #define MT_BBP_DFS_BASE 0x2a00
614 #define MT_BBP_TR_BASE 0x2b00
615 #define MT_BBP_CAL_BASE 0x2c00
616 #define MT_BBP_DSC_BASE 0x2e00
617 #define MT_BBP_PFMU_BASE 0x2f00
629 #define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0)
632 #define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0)
638 #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
641 #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)
643 #define MT_WCID_ADDR_BASE 0x1800
646 #define MT_SRAM_BASE 0x4000
648 #define MT_WCID_KEY_BASE 0x8000
651 #define MT_WCID_IV_BASE 0xa000
654 #define MT_WCID_ATTR_BASE 0xa800
657 #define MT_WCID_ATTR_PAIRWISE BIT(0)
666 #define MT_SKEY_BASE_0 0xac00
667 #define MT_SKEY_BASE_1 0xb400
672 #define MT_SKEY_MODE_BASE_0 0xb000
673 #define MT_SKEY_MODE_BASE_1 0xb3f0
677 #define MT_SKEY_MODE_MASK GENMASK(3, 0)
680 #define MT_BEACON_BASE 0xc000
682 #define MT_TEMP_SENSOR 0x1d000
683 #define MT_TEMP_SENSOR_VAL GENMASK(6, 0)